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GD16543-48BA Datasheet

  • GD16543-48BA

  • CLOCK/DATA RECOVERY|QFP|48PIN|PLASTIC

  • 9頁

  • ETC

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an Intel company
2.5 Gbit/s
Clock and Data
Recovery Circuit
GD16543
Preliminary
General Description
The GD16543 is a high performance
monolithic integrated
Clock and Data Re-
covery
(CDR) device applicable for opti-
cal communication systems including:
u
SDH STM-16
u
SONET OC-48
The CDR contains all circuits needed for
reliable acquisition and lock of the VCO
phase to the incoming data-stream.
The electrical input sensitivity is better
than 20 mV. Optical receivers with sensi-
tivity better than -34 dBm have been ob-
tained without optical pre-amplifiers.
The device meets all ITU-T jitter require-
ments when used with the recommended
loop filter (jitter tolerance, -transfer and
-generation).
The integrated 1:4 demultiplexer with dif-
ferential ECL outputs ensures a simple
and universal interface to the system
CMOS ASICs.
The 622 MHz output clock is maintained
within 500 ppm tolerance even in ab-
sence of data.
The GD16543 is available in a 40 lead
ceramic LCC and in a 48 lead 7x7 mm
TQFP power enhanced plastic package.
Features
l
Clock and Data Recovery covering
2.3 Gbit/s to 2.7 Gbit/s.
SDH STM-16, SONET OC-48
compatible.
Differential Data inputs with 20 mV
sensitivity.
Differential ECL Data and Clock
outputs.
Acquisition time: < 500
ms
Few external passive components
needed.
50
W
Loop-Through data inputs for
higher sensitivity.
Single supply operation.
Power dissipation: 1 W.
Available in:
鈥?a 48 lead 7x7 mm TQFP plastic
package
鈥?a 40 lead ceramic LCC.
l
l
l
l
l
l
l
Limiter
SIPO
SIPI
SINI
SINO
D
l
DOUT0
DOUN0
CK
Bang
Bang
Phase
Detector
l
DO
U
D
De-
MUX
DOUT1
DOUN1
DOUT2
DOUN2
DOUT3
DOUN3
CKOUT
CKOUN
MUX
REFXI
REFXO
R
V
Phase
D
Frequency
Detector
U
Applications
l
Change
Pump
VDD
VCO
VEE
VDDA
VEEA
RES
SEL1
SEL2
Lock
Detect
Clock and Data Recovery for optical
communication systems including:
鈥?SDH STM-16
鈥?SONET OC-48
LOCK
CHPO
VCTL
Data Sheet Rev.: 07

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