音影先锋亚洲天堂网|电影世界尽头的爱完整版播放|国产 熟女 91|高清无码免费观看欧美日韩|韩国一区二区三区黄色录像|美女亚洲加勒比在线|亚洲综合网 开心五月|7x成人在线入口|成人网站免费日韩毛片区|国产黄片?一级?二级?三级

GCIXF1002EDT Datasheet

  • GCIXF1002EDT

  • Controller Miscellaneous - Datasheet Reference

  • 128頁(yè)

  • ETC

掃碼查看芯片數(shù)據(jù)手冊(cè)

上傳產(chǎn)品規(guī)格書

PDF預(yù)覽

Intel
廬
IXF1002 Dual Port Gigabit
Ethernet Controller
Datasheet
Product Features
The Intel
廬
IXF1002 Dual Port Gigabit Ethernet Media Access Controller
(MAC), provides two independent 1000 Mb/s intelligent, high-performance
Media Access Control (MAC) ports. It includes Gigabit Physical Coding
Sublayer (GPCS) interface network management support and is optimized for
switch applications.
s
Integration
鈥?Offers two independent Ethernet 1000 Mb/s
MAC ports
鈥?Includes GPCS functions for 1000BASE-X
connections
鈥?Handles SNMP and RMON counters
s
Serial
鈥?Enables independent mode of operation in
each port
鈥?Supports IEEE 802.3x standard flow-control
functionality
鈥?Interfaces standard GPCS connections (10b
interface)
鈥?Interfaces standard GMII connections
鈥?Supports 1000BASE-SX, 1000BASE-LX,
1000BASE-CX, and 1000BASE-T
connections
鈥?Provides programmable CRC generation and
removal
鈥?Supports Auto-Negotiation link protocol for
1000BASE-X
鈥?Implements only full-duplex operation
鈥?Supports large packets of up to 64 Kbytes
s
IX Bus
鈥?Supports up to 5.12 Gbps memory bus
bandwidth
鈥?Variable bus speed of 33 MHz to 80 MHz
鈥?64-bit bus with three modes of operation:
鈥?Full 鈥?64 bits for transmit or receive
鈥?Split 鈥?2 low bits for receive, and 32 high
bits for transmit
鈥?Narrow 鈥?2 bits for transmit or receive
鈥?Independent 2 Kbyte transmit FIFO and 4
Kbyte receive FIFO for each port
鈥?Supports little or big endian byte ordering
鈥?Supports receive packet fragmentation on byte
boundaries (replay feature)
鈥?Programmable transmit and receive bus
thresholds
鈥?Enables optional appending of packet status
s
CPU Interface
鈥?Supports fully programmable independent
ports through a dedicated generic CPU port
鈥?Supports interrupt programming
鈥?Provides an 8- or 16-bit bus for register access
s
Performance
鈥?Packet transfers are completed prior to
servicing CPU interrupt requests
鈥?Enables early address filtering ability, with
packet header preprocessing
鈥?IEEE P802.1Q Virtual Bridged Local Area
Network (VLAN) tag append, strip and
replace function on chip, during packet
transmission
鈥?Offers ignore or stop transmission options
following packet transmission errors
鈥?Provides programmable automatic discard of
badly received packets such as cyclic
redundancy (CRC) errors and too long packets
鈥?Informs the system in case bad packets start to
appear on the FIFO bus
鈥?Allows interpacket gap (IPG) programming
s
Device
鈥?CPU and FIFO interfaces are compatible with
the IXF440 Multiport 10/100 Mbps Ethernet
Controller and the IXP1200 Network
Processor.
鈥?Includes internal and external loopback
capabilities
鈥?Provides software reset support
鈥?Supports JTAG boundary scan
鈥?Implemented in a low-power 3.3 V and 5 V
tolerant CMOS device
鈥?304-ESBGA package.
Notice:
This document contains preliminary information on new products in production. The
specifications are subject to change without notice. Verify with your local Intel sales office that
you have the latest datasheet before finalizing a design.
Order Number: 278310-008
June, 2002

GCIXF1002EDT相關(guān)型號(hào)PDF文件下載

您可能感興趣的PDF文件資料

熱門IC型號(hào)推薦

掃碼下載APP，
一鍵連接廣大的電子世界。

在線人工客服

買家服務(wù)：
賣家服務(wù)：
技術(shù)客服：

0571-85317607

網(wǎng)站技術(shù)支持

13606545031

客服在線時(shí)間周一至周五
9:00-17:30

關(guān)注官方微信號(hào)，
第一時(shí)間獲取資訊。

建議反饋
返回頂部

建議反饋

聯(lián)系人：

聯(lián)系方式：

按住滑塊，拖拽到最右邊
>>
感謝您向阿庫(kù)提出的寶貴意見，您的參與是維庫(kù)提升服務(wù)的動(dòng)力！意見一經(jīng)采納，將有感恩紅包奉上哦！