GAL26V12
High Performance E
2
CMOS PLD
Generic Array Logic
TM
FEATURES
鈥?HIGH PERFORMANCE E
2
CMOS
廬
TECHNOLOGY
鈥?7.5 ns Maximum Propagation Delay
鈥?Fmax = 142.8 MHz
鈥?4.5 ns Maximum from Clock Input to Data Output
鈥?TTL Compatible 16 mA Outputs
鈥?UltraMOS
廬
Advanced CMOS Technology
鈥?LOW POWER CMOS
鈥?90 mA Typical Icc
鈥?E CELL TECHNOLOGY
鈥?Reconfigurable Logic
鈥?Reprogrammable Cells
鈥?100% Tested/Guaranteed 100% Yields
鈥?High Speed Electrical Erasure (<100ms)
鈥?20 Year Data Retention
鈥?TWELVE OUTPUT LOGIC MACROCELLS
鈥?Maximum Flexibility for Complex Logic Designs
鈥?PRELOAD AND POWER-ON RESET OF REGISTERS
鈥?100% Functional Testability
鈥?APPLICATIONS INCLUDE:
鈥?DMA Control
鈥?State Machine Control
鈥?High Speed Graphics Processing
鈥?Standard Logic Speed Upgrade
鈥?ELECTRONIC SIGNATURE FOR IDENTIFICATION
INPUT
2
FUNCTIONAL BLOCK DIAGRAM
I/CLK 1
PRESET
INPUT
8
INPUT
8
INPUT
10
INPUT/CLK 2
12
INPUT
OLMC 0
OLMC 1
I/O/Q
I/O/Q
OLMC 2
I/O/Q
PROGRAMMABLE
AND-ARRAY
(150X52)
OLMC 3
14
I/O/Q
INPUT
OLMC 4
16
I/O/Q
INPUT
OLMC 5
16
I/O/Q
INPUT
OLMC 6
14
I/O/Q
INPUT
12
INPUT
10
INPUT
8
OLMC 7
I/O/Q
OLMC 8
OLMC 9
I/O/Q
I/O/Q
OLMC 10
8
I/O/Q
DESCRIPTION
The GAL26V12, at 7.5ns maximum propagation delay time, com-
bines a high performance CMOS process with Electrically Eras-
able (E
2
) floating gate technology to provide the highest perform-
ance available of any 26V12 device on the market. E
2
technol-
ogy offers high speed (<100ms) erase times, providing the ability
to reprogram or reconfigure the device quickly and efficiently.
The generic architecture provides maximum design flexibility by
allowing the Output Logic Macrocell (OLMC) to be configured by
the user. The GAL26V12 is fully function/fuse map/parametric
compatible with other 26V12 devices.
Unique test circuitry and reprogrammable cells allow complete
AC, DC, and functional testing during manufacture. As a result,
LATTICE is able to guarantee 100% field programmability and
functionality of all GAL
廬
products. LATTICE also guarantees 100
erase/rewrite cycles.
INPUT
OLMC 11
RESET
I/O/Q
PACKAGE DIAGRAMS
DIP
PLCC
I/CLK2
I
I
I/CLK1
I
I/O/Q
I/O/Q
I/CLK1
I
I
I/CLK2
I
1
28
I
I/O/Q
I/O/Q
I/O/Q
I
I
4
2
28
26
25
I
I
VCC
I
I
I
I
5
I/O/Q
I/O/Q
I/O/Q
I/O/Q
GND
I/O/Q
I/O/Q
I
Vcc
I
I
I
I
I
I
I
7
GAL
26V12
21
I/O/Q
I/O/Q
I/O/Q
GND
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
7
GAL26V12
Top View
23
9
21
11
12
14
16
19
18
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I
I
I
14
15
I/O/Q
Copyright 漏2000 Lattice Semiconductor Corp. GAL, E
2
CMOS and UltraMOS are registered trademarks of Lattice Semiconductor Corp. Generic Array Logic is a trademark of Lattice Semiconduc-
tor Corp. The specifications herein are subject to change without notice.
LATTICE SEMICONDUCTOR CORP., 5555 N.E. Moore Ct., Hillsboro, Oregon 97124 U.S.A.
Tel. (503) 268-8000 or 1-800-LATTICE; FAX (503) 268-8556
November 2000