音影先锋亚洲天堂网|电影世界尽头的爱完整版播放|国产 熟女 91|高清无码免费观看欧美日韩|韩国一区二区三区黄色录像|美女亚洲加勒比在线|亚洲综合网 开心五月|7x成人在线入口|成人网站免费日韩毛片区|国产黄片?一级?二级?三级

GAL22LV10D-4LJ Datasheet

  • GAL22LV10D-4LJ

  • Low Voltage E2CMOS PLD Generic Array Logic⑩

  • 218.10KB

  • 18頁

  • LATTICE   LATTICE

掃碼查看芯片數(shù)據(jù)手冊

上傳產(chǎn)品規(guī)格書

PDF預覽

FEATURES
New
Tole 5V
Inp rant
22Luts on
V10
D
GAL22LV10
Low Voltage E
2
CMOS PLD
Generic Array Logic鈩?/div>
FUNCTIONAL BLOCK DIAGRAM
I/CLK
RESET
鈥?HIGH PERFORMANCE E
2
CMOS
廬
TECHNOLOGY
鈥?4 ns Maximum Propagation Delay
鈥?Fmax = 250 MHz
鈥?3 ns Maximum from Clock Input to Data Output
鈥?UltraMOS
廬
Advanced CMOS Technology
鈥?3.3V LOW VOLTAGE 22V10 ARCHITECTURE
鈥?JEDEC-Compatible 3.3V Interface Standard
鈥?5V Compatible Inputs
鈥?I/O Interfaces with Standard 5V TTL Devices
(GAL22LV10C)
鈥?ACTIVE PULL-UPS ON ALL PINS (GAL22LV10D)
鈥?E
2
CELL TECHNOLOGY
鈥?Reconfigurable Logic
鈥?Reprogrammable Cells
鈥?100% Tested/100% Yields
鈥?High Speed Electrical Erasure (<100ms)
鈥?20 Year Data Retention
鈥?TEN OUTPUT LOGIC MACROCELLS
鈥?Maximum Flexibility for Complex Logic Designs
鈥?Programmable Output Polarity
鈥?PRELOAD AND POWER-ON RESET OF ALL REGISTERS
鈥?100% Functional Testability
鈥?APPLICATIONS INCLUDE:
鈥?Glue Logic for 3.3V Systems
鈥?DMA Control
鈥?State Machine Control
鈥?High Speed Graphics Processing
鈥?Standard Logic Speed Upgrade
鈥?ELECTRONIC SIGNATURE FOR IDENTIFICATION
DESCRIPTION
The GAL22LV10D, at 4 ns maximum propagation delay time,
provides the highest speed performance available in the PLD
market. The GAL22LV10C can interface with both 3.3V and 5V
signal levels. The GAL22LV10 is manufactured using Lattice
Semiconductor's advanced 3.3V E
2
CMOS process, which com-
bines CMOS with Electrically Erasable (E
2
) floating gate technol-
ogy. High speed erase times (<100ms) allow the devices to be
reprogrammed quickly and efficiently.
The generic architecture provides maximum design flexibility by
allowing the Output Logic Macrocell (OLMC) to be configured by
the user.
Unique test circuitry and reprogrammable cells allow complete
AC, DC, and functional testing during manufacture. As a result,
Lattice Semiconductor delivers 100% field programmability and
functionality of all GAL products. In addition, 100 erase/write
cycles and data retention in excess of 20 years are specified.
8
OLMC
I/O/Q
I
10
OLMC
I
12
I/O/Q
I
OLMC
I/O/Q
PROGRAMMABLE
AND-ARRAY
(132X44)
14
OLMC
I
I/O/Q
16
OLMC
I
I/O/Q
I
16
OLMC
I/O/Q
I
14
OLMC
I/O/Q
I
12
OLMC
I/O/Q
I
10
OLMC
I/O/Q
I
8
OLMC
I/O/Q
I
PRESET
PIN CONFIGURATION
PLCC
I/CLK
I/O/Q
Vcc
NC
I/O/Q
26
25
I/O/Q
I/O/Q
7
23
I
4
I
I
I
NC
I
I
I
11
12
I
9
5
I
2
28
GAL22LV10
Top View
I/O/Q
NC
21
I/O/Q
I/O/Q
14
I
GND
NC
16
I
I/O/Q
19
18
I/O/Q
I/O/Q
Copyright 漏 1997 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject
to change without notice.
LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A.
Tel. (503) 681-0118; 1-888-ISP-PLDS; FAX (503) 681-3037; http://www.latticesemi.com
July 1997
22lv10_03
1

GAL22LV10D-4LJ 產(chǎn)品屬性

  • Lattice

  • SPLD - 簡單可編程邏輯器件

  • GAL

  • 10

  • 250 MHz

  • 10

  • 4 ns

  • 3.3 V

  • 130 mA

  • + 75 C

  • 0 C

  • PLCC-28

  • SMD/SMT

  • Tube

  • 370

  • 3.6 V

  • 3 V

GAL22LV10D-4LJ相關型號PDF文件下載

掃碼下載APP，
一鍵連接廣大的電子世界。

在線人工客服

買家服務：
賣家服務：
技術客服：

0571-85317607

網(wǎng)站技術支持

13606545031

客服在線時間周一至周五
9:00-17:30

關注官方微信號，
第一時間獲取資訊。

建議反饋

聯(lián)系人：

聯(lián)系方式：

按住滑塊，拖拽到最右邊
>>
感謝您向阿庫提出的寶貴意見，您的參與是維庫提升服務的動力！意見一經(jīng)采納，將有感恩紅包奉上哦！