音影先锋亚洲天堂网|电影世界尽头的爱完整版播放|国产 熟女 91|高清无码免费观看欧美日韩|韩国一区二区三区黄色录像|美女亚洲加勒比在线|亚洲综合网 开心五月|7x成人在线入口|成人网站免费日韩毛片区|国产黄片?一级?二级?三级

GAL20XV10B-10LJ Datasheet

  • GAL20XV10B-10LJ

  • High-Speed E2CMOS PLD Generic Array Logic

  • 235.69KB

  • 14頁

  • LATTICE   LATTICE

掃碼查看芯片數(shù)據(jù)手冊

上傳產(chǎn)品規(guī)格書

PDF預(yù)覽

GAL20XV10
High-Speed E
2
CMOS PLD
Generic Array Logic鈩?/div>
Features
鈥?HIGH PERFORMANCE E
2
CMOS
廬
TECHNOLOGY
鈥?10 ns Maximum Propagation Delay
鈥?Fmax = 100 MHz
鈥?7 ns Maximum from Clock Input to Data Output
鈥?TTL Compatible 16 mA Outputs
鈥?UltraMOS
廬
Advanced CMOS Technology
鈥?50% to 75% REDUCTION IN POWER FROM BIPOLAR
鈥?90mA Maximum Icc
鈥?75mA Typical Icc
鈥?ACTIVE PULL-UPS ON ALL PINS
鈥?E
2
CELL TECHNOLOGY
鈥?Reconfigurable Logic
鈥?Reprogrammable Cells
鈥?100% Tested/100% Yields
鈥?High Speed Electrical Erasure (<100 ms)
鈥?20 Year Data Retention
鈥?TEN OUTPUT LOGIC MACROCELLS
鈥?XOR Gate Capability on all Outputs
鈥?Full Function and Parametric Compatibility with
PAL12L10, 20L10, 20X10, 20X8, 20X4
鈥?Registered or Combinatorial with Polarity
鈥?PRELOAD AND POWER-ON RESET OF ALL REGISTERS
鈥?APPLICATIONS INCLUDE:
鈥?High Speed Counters
鈥?Graphics Processing
鈥?Comparators
鈥?ELECTRONIC SIGNATURE FOR IDENTIFICATION
Functional Block Diagram
I/CLK
4
OLMC
I/O/Q
I
4
OLMC
I
4
I/O/Q
I
OLMC
I/O/Q
PROGRAMMABLE
AND-ARRAY
(40 X 40)
4
OLMC
I
I/O/Q
4
OLMC
I
I/O/Q
I
4
OLMC
I/O/Q
I
4
OLMC
I/O/Q
I
4
OLMC
I/O/Q
I
4
OLMC
I/O/Q
I
4
OLMC
I/O/Q
Description
The GAL20XV10 combines a high performance CMOS process
with electrically erasable (E
2
) floating gate technology to provide
the highest speed Exclusive-OR PLD available in the market. At
90mA maximum Icc (75mA typical Icc), the GAL20XV10 provides
a substantial savings in power when compared to bipolar counter-
parts. E
2
CMOS technology offers high speed (<100ms) erase
times providing the ability to reprogram, reconfigure or test the de-
vices quickly and efficiently.
The generic architecture provides maximum design flexibility by
allowing the Output Logic Macrocell (OLMC) to be configured by
the user. An important subset of the many architecture configu-
rations possible with the GAL20XV10 are the PAL
廬
architectures
listed in the macrocell description section of this document. The
GAL20XV10 is capable of emulating these PAL architectures with
full function and parametric compatibility.
Unique test circuitry and reprogrammable cells allow complete AC,
DC, and functional testing during manufacturing. As a result, Lattice
Semiconductor delivers 100% field programmability and function-
ality of all GAL products. In addition, 100 erase/write cycles and
data retention in excess of 20 years are specified.
I/OE
Pin Configuration
DIP
PLCC
I/CLK
I/CLK
I/O/Q
Vcc
I/O/Q
1
24
Vcc
I/O/Q
I/O/Q
I
I
25
I/O/Q
I/O/Q
I
I
NC
4
I
I
I
NC
I
I
I
11
12
I
I
2
28
26
5
I
I
I
I
I
I
I
I
GND
12
6
GAL
20XV10
I/O/Q
I/O/Q
I/O/Q
7
GAL20XV10
Top View
14
GND
NC
23
I/O/Q
NC
9
21
I/O/Q
I/O/Q
18
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
19
16
I/O/Q
I/OE
I/O/Q
18
I/O/Q
13
I/OE
Copyright 漏 1997 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject
to change without notice.
LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A.
Tel. (503) 681-0118; 1-888-ISP-PLDS; FAX (503) 681-3037; http://www.latticesemi.com
July 1997
20xv10_02
1

GAL20XV10B-10LJ 產(chǎn)品屬性

  • Lattice

  • SPLD - 簡單可編程邏輯器件

  • GAL

  • 10

  • 100 MHz

  • 10

  • 10 ns

  • 5 V

  • 90 mA

  • + 75 C

  • 0 C

  • PLCC-28

  • SMD/SMT

  • 4

  • Tube / Tray

  • 37

  • 5.25 V

  • 4.75 V

GAL20XV10B-10LJ相關(guān)型號PDF文件下載

掃碼下載APP，
一鍵連接廣大的電子世界。

在線人工客服

買家服務(wù)：
賣家服務(wù)：
技術(shù)客服：

0571-85317607

網(wǎng)站技術(shù)支持

13606545031

客服在線時間周一至周五
9:00-17:30

關(guān)注官方微信號，
第一時間獲取資訊。

建議反饋

聯(lián)系人：

聯(lián)系方式：

按住滑塊，拖拽到最右邊
>>
感謝您向阿庫提出的寶貴意見，您的參與是維庫提升服務(wù)的動力！意見一經(jīng)采納，將有感恩紅包奉上哦！