音影先锋亚洲天堂网|电影世界尽头的爱完整版播放|国产 熟女 91|高清无码免费观看欧美日韩|韩国一区二区三区黄色录像|美女亚洲加勒比在线|亚洲综合网 开心五月|7x成人在线入口|成人网站免费日韩毛片区|国产黄片?一级?二级?三级

GAL20VP8B-25LJ Datasheet

  • GAL20VP8B-25LJ

  • High-Speed E2CMOS PLD Generic Array Logic

  • 17頁

  • LATTICE   LATTICE

掃碼查看芯片數(shù)據(jù)手冊

上傳產品規(guī)格書

PDF預覽

GAL20VP8
High-Speed E
2
CMOS PLD
Generic Array Logic鈩?/div>
Features
鈥?HIGH DRIVE E
2
CMOS
廬
GAL
廬
DEVICE
鈥?TTL Compatible 64 mA Output Drive
鈥?15 ns Maximum Propagation Delay
鈥?Fmax = 80 MHz
鈥?10 ns Maximum from Clock Input to Data Output
鈥?UltraMOS
廬
Advanced CMOS Technology
鈥?ENHANCED INPUT AND OUTPUT FEATURES
鈥?Schmitt Trigger Inputs
鈥?Programmable Open-Drain or Totem-Pole Outputs
鈥?Active Pull-Ups on All Inputs and I/O pins
鈥?E
2
CELL TECHNOLOGY
鈥?Reconfigurable Logic
鈥?Reprogrammable Cells
鈥?100% Tested/100% Yields
鈥?High Speed Electrical Erasure (<100ms)
鈥?20 Year Data Retention
鈥?EIGHT OUTPUT LOGIC MACROCELLS
鈥?Maximum Flexibility for Complex Logic Designs
鈥?Programmable Output Polarity
鈥?Architecturally Compatible with Standard GAL20V8
鈥?PRELOAD AND POWER-ON RESET OF ALL REGISTERS
鈥?100% Functional Testability
鈥?APPLICATIONS INCLUDE:
鈥?Ideal for Bus Control & Bus Arbitration Logic
鈥?Bus Address Decode Logic
鈥?Memory Address, Data and Control Circuits
鈥?DMA Control
鈥?ELECTRONIC SIGNATURE FOR IDENTIFICATION
I
8
I
OLMC
I/O/Q
Functional Block Diagram
I/CLK
I
I
IMUX
CLK
8
OLMC
I/O/Q
PROGRAMMABLE
AND-ARRAY
(64 X 40)
8
OLMC
I/O/Q
I
8
OLMC
I/O/Q
I
8
OLMC
I/O/Q
I
8
OLMC
I/O/Q
I
8
I
8
OLMC
OE
OLMC
I/O/Q
I/O/Q
I
I
I
IMUX
I/OE
Description
The GAL20VP8, with 64 mA drive capability and 15 ns maximum
propagation delay time is ideal for Bus and Memory control appli-
cations.
The GAL20VP8 is manufactured using Lattice
Semiconductor's advanced E
2
CMOS process which combines
CMOS with Electrically Erasable (E
2
) floating gate technology. High
speed erase times (<100ms) allow the devices to be reprogrammed
quickly and efficiently.
System bus and memory interfaces require control logic before
driving the bus or memory interface signals. The GAL20VP8
combines the familiar GAL20V8 architecture with bus drivers as
its outputs. The generic architecture provides maximum design flex-
ibility by allowing the Output Logic Macrocell (OLMC) to be con-
figured by the user. The 64mA output drive eliminates the need for
additional devices to provide bus-driving capability.
Unique test circuitry and reprogrammable cells allow complete AC,
DC, and functional testing during manufacture. As a result,
Lattice Semiconductor delivers 100% field programmability and
functionality of all GAL products. In addition, 100 erase/write cycles
and data retention in excess of 20 years are specified.
Pin Configuration
PLCC
I/CLK
I/CLK
I/O/Q
NC
DIP
1
24
I
I
I/O/Q
I
I
25
I/O/Q
I/O/Q
I
I
28
4
I
I
Vcc
NC
I
I
I
11
12
9
7
5
I
2
I
26
I
I
Vcc
I
I
I
I
I
I/OE
12
6
GAL
20VP8
18
I/O/Q
I/O/Q
I/O/Q
GND
I/O/Q
I/O/Q
I/O/Q
I/O/Q
13
I
GAL20VP8
Top View
14
16
23
I/O/Q
NC
21
GND
I/O/Q
19
18
I/O/Q
I/OE
I/O/Q
Copyright 漏 1997 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject
to change without notice.
I/O/Q
I
I
NC
I
LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A.
Tel. (503) 268-8000; 1-800-LATTICE; FAX (503) 268-8556; http://www.latticesemi.com
December 1997
20vp8_03
1

GAL20VP8B-25LJ 產品屬性

  • Lattice

  • SPLD - 簡單可編程邏輯器件

  • GAL

  • 8

  • 50 MHz

  • 8

  • 25 ns

  • 5 V

  • 115 mA

  • + 75 C

  • 0 C

  • PLCC-28

  • SMD/SMT

  • 8

  • 37

  • 5.25 V

  • 4.75 V

GAL20VP8B-25LJ相關型號PDF文件下載

掃碼下載APP，
一鍵連接廣大的電子世界。

在線人工客服

買家服務：
賣家服務：
技術客服：

0571-85317607

網(wǎng)站技術支持

13606545031

客服在線時間周一至周五
9:00-17:30

關注官方微信號，
第一時間獲取資訊。

建議反饋

聯(lián)系人：

聯(lián)系方式：

按住滑塊，拖拽到最右邊
>>
感謝您向阿庫提出的寶貴意見，您的參與是維庫提升服務的動力！意見一經(jīng)采納，將有感恩紅包奉上哦！