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GAL20V8B-15QJN Datasheet

  • GAL20V8B-15QJN

  • High Performance E2CMOS PLD Generic Array Logic⑩

  • 25頁

  • LATTICE   LATTICE

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ree
Lead-F ge
P a c k a ns
Optio le!
b
Availa
GAL20V8
High Performance E
2
CMOS PLD
Generic Array Logic鈩?/div>
Features
鈥?HIGH PERFORMANCE E
2
CMOS
廬
TECHNOLOGY
鈥?5 ns Maximum Propagation Delay
鈥?Fmax = 166 MHz
鈥?4 ns Maximum from Clock Input to Data Output
鈥?UltraMOS
廬
Advanced CMOS Technology
鈥?50% to 75% REDUCTION IN POWER FROM BIPOLAR
鈥?75mA Typ Icc on Low Power Device
鈥?45mA Typ Icc on Quarter Power Device
鈥?ACTIVE PULL-UPS ON ALL PINS
鈥?E
2
CELL TECHNOLOGY
鈥?Reconfigurable Logic
鈥?Reprogrammable Cells
鈥?100% Tested/100% Yields
鈥?High Speed Electrical Erasure (<100ms)
鈥?20 Year Data Retention
鈥?EIGHT OUTPUT LOGIC MACROCELLS
鈥?Maximum Flexibility for Complex Logic Designs
鈥?Programmable Output Polarity
鈥?Also Emulates 24-pin PAL
廬
Devices with Full Function/
Fuse Map/Parametric Compatibility
鈥?PRELOAD AND POWER-ON RESET OF ALL REGISTERS
鈥?100% Functional Testability
鈥?APPLICATIONS INCLUDE:
鈥?DMA Control
鈥?State Machine Control
鈥?High Speed Graphics Processing
鈥?Standard Logic Speed Upgrade
鈥?ELECTRONIC SIGNATURE FOR IDENTIFICATION
鈥?LEAD-FREE PACKAGE OPTIONS
Functional Block Diagram
I/CLK
I
I
IMUX
CLK
8
OLMC
I
8
I
OLMC
I/O/Q
Select devices have been discontinued.
See Ordering Information section for product status.
I/O/Q
PROGRAMMABLE
AND-ARRAY
(64 X 40)
8
OLMC
I/O/Q
I
8
OLMC
I/O/Q
I
8
OLMC
I/O/Q
I
8
OLMC
I/O/Q
I
8
OLMC
I
8
I/O/Q
OE
I/O/Q
I
I
OLMC
I
IMUX
I/OE
Description
The GAL20V8C, at 5ns maximum propagation delay time, com-
bines a high performance CMOS process with Electrically Eras-
able (E
2
) floating gate technology to provide the highest speed
performance available in the PLD market. High speed erase times
(<100ms) allow the devices to be reprogrammed quickly and ef-
ficiently.
The generic architecture provides maximum design flexibility by
allowing the Output Logic Macrocell (OLMC) to be configured by
the user. An important subset of the many architecture configura-
tions possible with the GAL20V8 are the PAL architectures listed
in the table of the macrocell description section. GAL20V8 devices
are capable of emulating any of these PAL architectures with full
function/fuse map/parametric compatibility.
Unique test circuitry and reprogrammable cells allow complete AC,
DC, and functional testing during manufacture. As a result, Lattice
Semiconductor delivers 100% field programmability and function-
ality of all GAL products. In addition, 100 erase/write cycles and
data retention in excess of 20 years are specified.
Pin Configuration
DIP
PLCC
I/CLK
I/CLK
Vcc
NC
I/O/Q
1
24
Vcc
I
I
I
I/O/Q
I/O/Q
4
I
I
I
NC
I
I
I
11
12
9
7
5
2
28
26
25
I
I
I
I
I
I
I
I
GND
12
6
GAL
20V8
I/O/Q
I/O/Q
I/O/Q
I/O/Q
18
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I
13
I/OE
I
I
I
GAL20V8
Top View
23
I/O/Q
NC
21
I/O/Q
I/O/Q
14
16
19
18
I/O/Q
I
I
GND
NC
I/OE
I
Copyright 漏 2006 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject
to change without notice.
I/O/Q
LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A.
Tel. (503) 268-8000; 1-800-LATTICE; FAX (503) 268-8556; http://www.latticesemi.com
August 2006
20v8_07
1

GAL20V8B-15QJN 產(chǎn)品屬性

  • 37

  • 集成電路 (IC)

  • 嵌入式 - CPLD（復(fù)雜可編程邏輯器件）

  • GAL®20V8

  • EE PLD

  • 15.0ns

  • 4.75 V ~ 5.25 V

  • -

  • 8

  • -

  • -

  • 0°C ~ 75°C

  • 表面貼裝

  • 28-LCC（J 形引線）

  • 28-PLCC（11.51x11.51）

  • 管件

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