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GAL20V8Z

GAL20V8ZD

Zero Power E

2

CMOS PLD

Features

鈥?ZERO POWER E

2

CMOS TECHNOLOGY

鈥?100

碌

A Standby Current

鈥?Input Transition Detection on GAL20V8Z

鈥?Dedicated Power-down Pin on GAL20V8ZD

鈥?Input and Output Latching During Power Down

鈥?HIGH PERFORMANCE E

2

CMOS TECHNOLOGY

鈥?12 ns Maximum Propagation Delay

鈥?Fmax = 83.3 MHz

鈥?8 ns Maximum from Clock Input to Data Output

鈥?TTL Compatible 16 mA Output Drive

鈥?UltraMOS

廬

Advanced CMOS Technology

鈥?E CELL TECHNOLOGY

鈥?Reconfigurable Logic

鈥?Reprogrammable Cells

鈥?100% Tested/100% Yields

鈥?High Speed Electrical Erasure (<100ms)

鈥?20 Year Data Retention

鈥?EIGHT OUTPUT LOGIC MACROCELLS

鈥?Maximum Flexibility for Complex Logic Designs

鈥?Programmable Output Polarity

鈥?Architecturally Similar to Standard GAL20V8

鈥?PRELOAD AND POWER-ON RESET OF ALL REGISTERS

鈥?100% Functional Testability

鈥?APPLICATIONS INCLUDE:

鈥?Battery Powered Systems

鈥?DMA Control

鈥?State Machine Control

鈥?High Speed Graphics Processing

鈥?ELECTRONIC SIGNATURE FOR IDENTIFICATION

I

8

OLMC

OE

Functional Block Diagram

I/CLK

I

I

8

I

8

I/DPP

OLMC

IMUX

CLK

OLMC

I/O/Q

I/O/Q

PROGRAMMABLE

AND-ARRAY

(64 X 40)

8

OLMC

I/O/Q

2

I

8

OLMC

I/O/Q

I

8

OLMC

I/O/Q

I

8

OLMC

I/O/Q

I

8

I/O/Q

OLMC

I

I

I/O/Q

I

IMUX

I/OE

Description

The GAL20V8Z and GAL20V8ZD, at 100

碌A(chǔ)

standby current and

12ns propagation delay provides the highest speed and lowest

power combination PLD available in the market. The

GAL20V8Z/ZD is manufactured using Lattice Semiconductor's ad-

vanced zero power E

2

CMOS process, which combines CMOS with

Electrically Erasable (E

2

) floating gate technology.

The GAL20V8Z uses Input Transition Detection (ITD) to put the

device in standby mode and is capable of emulating the full func-

tionality of the standard GAL20V8. The GAL20V8ZD utilizes a

dedicated power-down pin (DPP) to put the device in standby mode.

It has 19 inputs available to the AND array.

Unique test circuitry and reprogrammable cells allow complete AC,

DC, and functional testing during manufacture. As a result, Lattice

Semiconductor delivers 100% field programmability and function-

ality of all GAL products. In addition, 100 erase/write cycles and

data retention in excess of 20 years are specified.

Pin Configuration

DIP

PLCC

I/CLK

I/O/Q

Vcc

NC

I

I

I

I/C LK

I

I

25

I/O/Q

I/O/Q

23

I/O/Q

NC

21

1

2

3

4

5

6

7

8

9

10

11

12

24

23

Vcc

I

I/ O/ Q

I/ O/ Q

I/ O/ Q

I/ O/ Q

4

I/DPP

I

I

NC

7

5

2

28

26

I/D P P

I

I

I

I

I

9

GAL20V8Z

GAL20V8ZD

Top View

12

I

I

GAL

20V8Z

20V8ZD

22

21

20

19

I

I

I

I

I

GND

18

17

16

15

14

13

I/O/Q

I/O/Q

I/ O/ Q

I/ O/ Q

I

I /O E

I/O/Q

I/O/Q

11

14

NC

GND

16

I/OE

I

18

I/O/Q

19

I/O/Q

Copyright 漏 1997 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject

to change without notice.

LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A.

Tel. (503) 268-8000; 1-800-LATTICE; FAX (503) 268-8556; http://www.latticesemi.com

December 1997

20v8zzd_03

1

next

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