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GAL20RA10B-7LJ Datasheet

  • GAL20RA10B-7LJ

  • High-Speed Asynchronous E2CMOS PLD Generic Array Logic⑩

  • 241.63KB

  • 15頁

  • LATTICE   LATTICE

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GAL20RA10
High-Speed Asynchronous E
2
CMOS PLD
Generic Array Logic鈩?/div>
Features
鈥?HIGH PERFORMANCE E
2
CMOS
廬
TECHNOLOGY
鈥?7.5 ns Maximum Propagation Delay
鈥?Fmax = 83.3 MHz
鈥?9 ns Maximum from Clock Input to Data Output
鈥?TTL Compatible 8 mA Outputs
鈥?UltraMOS
廬
Advanced CMOS Technology
鈥?50% to 75% REDUCTION IN POWER FROM BIPOLAR
鈥?75mA Typical Icc
鈥?ACTIVE PULL-UPS ON ALL PINS
鈥?E
2
CELL TECHNOLOGY
鈥?Reconfigurable Logic
鈥?Reprogrammable Cells
鈥?100% Tested/100% Yields
鈥?High Speed Electrical Erasure (<100 ms)
鈥?20 Year Data Retention
鈥?TEN OUTPUT LOGIC MACROCELLS
鈥?Independent Programmable Clocks
鈥?Independent Asynchronous Reset and Preset
鈥?Registered or Combinatorial with Polarity
鈥?Full Function and Parametric Compatibility with
PAL20RA10
鈥?PRELOAD AND POWER-ON RESET OF ALL REGISTERS
鈥?100% Functional Testability
鈥?APPLICATIONS INCLUDE:
鈥?State Machine Control
鈥?Standard Logic Consolidation
鈥?Multiple Clock Logic Designs
鈥?ELECTRONIC SIGNATURE FOR IDENTIFICATION
Functional Block Diagram
PL
8
I
OLMC
I/O/Q
8
I
OLMC
I/O/Q
8
I
OLMC
I/O/Q
PROGRAMMABLE
AND-ARRAY
(80X40)
8
OLMC
I
I/O/Q
8
OLMC
I
I/O/Q
8
OLMC
I
I/O/Q
8
OLMC
I
I/O/Q
8
I
OLMC
I/O/Q
8
I
OLMC
I/O/Q
8
I
OLMC
I/O/Q
Description
The GAL20RA10 combines a high performance CMOS process
with electrically erasable (E
2
) floating gate technology to provide
the highest speed performance available in the PLD market. Lattice
Semiconductor鈥檚 E
2
CMOS circuitry achieves power levels as low
as 75mA typical I
CC
which represents a substantial savings in power
when compared to bipolar counterparts. E
2
technology offers high
speed (<100ms) erase times providing the ability to reprogram,
reconfigure or test the devices quickly and efficiently.
The generic architecture provides maximum design flexibility by
allowing the Output Logic Macrocell (OLMC) to be configured by
the user. The GAL20RA10 is a direct parametric compatible CMOS
replacement for the PAL20RA10 device.
Unique test circuitry and reprogrammable cells allow complete AC,
DC, and functional testing during manufacturing. Therefore, Lattice
Semiconductor delivers 100% field programmability and function-
ality of all GAL products. In addition, 100 erase/write cycles and
data retention in excess of 20 years are specified.
OE
Pin Configuration
DIP
PLCC
I/O/Q
I/O/Q
Vcc
PL
NC
PL
I
I
I
25
I/O/Q
I/O/Q
1
24
Vcc
I/O/Q
I/O/Q
4
I
I
I
NC
I
I
I
11
12
9
7
5
2
28
26
I
I
I
I
I
I
I
GND
GAL
20RA10
6
18
I
I
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
GAL20RA10
Top View
14
16
23
I/O/Q
NC
21
I/O/Q
I/O/Q
19
18
I/O/Q
GND
OE
I
I
I/O/Q
I/O/Q
NC
12
13
OE
Copyright 漏 1997 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject
to change without notice.
LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A.
Tel. (503) 681-0118; 1-888-ISP-PLDS; FAX (503) 681-3037; http://www.latticesemi.com
July 1997
20ra10_02
1

GAL20RA10B-7LJ 產品屬性

  • Lattice

  • SPLD - 簡單可編程邏輯器件

  • GAL

  • 10

  • 83.3 MHz

  • 10

  • 7.5 ns

  • 5 V

  • 100 mA

  • + 75 C

  • 0 C

  • PLCC-28

  • SMD/SMT

  • Tube

  • 370

  • 5.25 V

  • 4.75 V

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