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GAL20LV8D-5LJ Datasheet

  • GAL20LV8D-5LJ

  • Low Voltage E2CMOS PLD Generic Array Logic

  • 284.64KB

  • 17頁

  • LATTICE   LATTICE

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Ne
Tolew 5V
Inp rant
u
20L ts on
V8D
Features
鈥?HIGH PERFORMANCE E
2
CMOS
廬
TECHNOLOGY
鈥?3.5 ns Maximum Propagation Delay
鈥?Fmax = 250 MHz
鈥?2.5 ns Maximum from Clock Input to Data Output
鈥?UltraMOS
廬
Advanced CMOS Technology
鈥?TTL-Compatible Balanced 8mA Output Drive
鈥?3.3V LOW VOLTAGE 20V8 ARCHITECTURE
鈥?JEDEC-Compatible 3.3V Interface Standard
鈥?5V Compatible Inputs
鈥?ACTIVE PULL-UPS ON ALL PINS
鈥?E
2
CELL TECHNOLOGY
鈥?Reconfigurable Logic
鈥?Reprogrammable Cells
鈥?100% Tested/100% Yields
鈥?High Speed Electrical Erasure (<100ms)
鈥?20 Year Data Retention
鈥?EIGHT OUTPUT LOGIC MACROCELLS
鈥?Maximum Flexibility for Complex Logic Designs
鈥?Programmable Output Polarity
鈥?PRELOAD AND POWER-ON RESET OF ALL REGISTERS
鈥?100% Functional Testability
鈥?APPLICATIONS INCLUDE:
鈥?Glue Logic for 3.3V Systems
鈥?DMA Control
鈥?State Machine Control
鈥?High Speed Graphics Processing
鈥?Standard Logic Speed Upgrade
鈥?ELECTRONIC SIGNATURE FOR IDENTIFICATION
I
GAL20LV8
Low Voltage E
2
CMOS PLD
Generic Array Logic鈩?/div>
Functional Block Diagram
I/CLK
I
I
8
I
8
I
OLMC
I/O/Q
IMUX
CLK
OLMC
I/O/Q
PROGRAMMABLE
AND-ARRAY
(64 X 40)
8
OLMC
I/O/Q
8
OLMC
I/O/Q
I
8
OLMC
I/O/Q
I
8
OLMC
I/O/Q
I
8
I
8
OLMC
OE
OLMC
I/O/Q
I
I
I/O/Q
I
IMUX
I/OE
Description
The GAL20LV8D, at 3.5 ns maximum propagation delay time,
provides the highest speed performance available in the PLD
market. The GAL20LV8D is manufactured using Lattice
Semiconductor's advanced 3.3V E
2
CMOS process, which com-
bines CMOS with Electrically Erasable (E
2
) floating gate technology.
High speed erase times (<100ms) allow the devices to be repro-
grammed quickly and efficiently.
The generic architecture provides maximum design flexibility by
allowing the Output Logic Macrocell (OLMC) to be configured by
the user. An important subset of the many architecture configura-
tions possible with the GAL20LV8D are the PAL architectures listed
in the table of the macrocell description section. GAL20LV8D
devices are capable of emulating any of these PAL architectures
with full function/fuse map compatibility.
Unique test circuitry and reprogrammable cells allow complete AC,
DC, and functional testing during manufacture. As a result, Lattice
Semiconductor delivers 100% field programmability and function-
ality of all GAL products. In addition, 100 erase/write cycles and
data retention in excess of 20 years are specified.
Pin Configuration
PLCC
I/CLK
Vcc
NC
I/O/Q
26
25
I
4
I
I
I
NC
I
I
I
11
12
9
7
5
I
2
28
I
I/O/Q
I/O/Q
GAL20LV8D
Top View
23
I/O/Q
NC
21
I/O/Q
I/O/Q
14
16
19
18
I/O/Q
I
I
NC
GND
I/OE
I
Copyright 漏 2000 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject
to change without notice.
I/O/Q
LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A.
Tel. (503) 268-8000; 1-800-LATTICE; FAX (503) 268-8556; http://www.latticesemi.com
March 2000
20lv8_05
1

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