音影先锋亚洲天堂网|电影世界尽头的爱完整版播放|国产 熟女 91|高清无码免费观看欧美日韩|韩国一区二区三区黄色录像|美女亚洲加勒比在线|亚洲综合网 开心五月|7x成人在线入口|成人网站免费日韩毛片区|国产黄片?一级?二级?三级

GAL18V10-20LP Datasheet

  • GAL18V10-20LP

  • High Performance E2CMOS PLD Generic Array Logic

  • 16頁(yè)

  • LATTICE   LATTICE

掃碼查看芯片數(shù)據(jù)手冊(cè)

上傳產(chǎn)品規(guī)格書(shū)

PDF預(yù)覽

GAL18V10
High Performance E
2
CMOS PLD
Generic Array Logic鈩?/div>
Features
鈥?HIGH PERFORMANCE E
2
CMOS
廬
TECHNOLOGY
鈥?7.5 ns Maximum Propagation Delay
鈥?Fmax = 111 MHz
鈥?5.5 ns Maximum from Clock Input to Data Output
鈥?TTL Compatible 16 mA Outputs
鈥?UltraMOS
廬
Advanced CMOS Technology
鈥?LOW POWER CMOS
鈥?75 mA Typical Icc
鈥?ACTIVE PULL-UPS ON ALL PINS
鈥?E CELL TECHNOLOGY
鈥?Reconfigurable Logic
鈥?Reprogrammable Cells
鈥?100% Tested/100% Yields
鈥?High Speed Electrical Erasure (<100ms)
鈥?20 Year Data Retention
鈥?TEN OUTPUT LOGIC MACROCELLS
鈥?Uses Standard 22V10 Macrocell Architecture
鈥?Maximum Flexibility for Complex Logic Designs
鈥?PRELOAD AND POWER-ON RESET OF REGISTERS
鈥?100% Functional Testability
鈥?APPLICATIONS INCLUDE:
鈥?DMA Control
鈥?State Machine Control
鈥?High Speed Graphics Processing
鈥?Standard Logic Speed Upgrade
鈥?ELECTRONIC SIGNATURE FOR IDENTIFICATION
8
Functional Block Diagram
I/CLK
RESET
8
OLMC
I/O/Q
I
8
OLMC
I/O/Q
8
OLMC
2
I
I/O/Q
PROGRAMMABLE
AND-ARRAY
(96X36)
8
OLMC
I/O/Q
I
10
OLMC
I/O/Q
10
OLMC
I
I/O/Q
8
OLMC
I/O/Q
I
8
OLMC
I/O/Q
I
8
OLMC
I/O/Q
Description
The GAL18V10, at 7.5 ns maximum propagation delay time, com-
bines a high performance CMOS process with Electrically Eras-
able (E
2
) floating gate technology to provide a very flexible 20-pin
PLD. CMOS circuitry allows the GAL18V10 to consume much less
power when compared to its bipolar counterparts. The E
2
technol-
ogy offers high speed (<100ms) erase times, providing the ability
to reprogram or reconfigure the device quickly and efficiently.
By building on the popular 22V10 architecture, the GAL18V10
eliminates the learning curve usually associated with using a new
device architecture. The generic architecture provides maximum
design flexibility by allowing the Output Logic Macrocell (OLMC)
to be configured by the user. The GAL18V10 OLMC is fully com-
patible with the OLMC in standard bipolar and CMOS 22V10 de-
vices.
Unique test circuitry and reprogrammable cells allow complete AC,
DC, and functional testing during manufacture. As a result, Lattice
Semiconductor delivers 100% field programmability and function-
ality of all GAL products. In addition, 100 erase/write cycles and
data retention in excess of 20 years are specified.
OLMC
I/O/Q
I
PRESET
Pin Configuration
DIP
PLCC
I
I
2
I
I
I
I
I
8
6
4
I/CLK Vcc
20
18
I/O/Q
I/O/Q
I/CLK
I
I
I
I/O/Q
1
20
Vcc
I/O/Q
GAL
18V10
5
15
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
GAL18V10
Top View
16
I/O/Q
I/O/Q
I
I
I
I
I/O/Q
GND
14
9
11
13
I/O/Q
I/O/Q GND I/O/Q I/O/Q I/O/Q
10
11
I/O/Q
Copyright 漏 1997 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject
to change without notice.
LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A.
Tel. (503) 681-0118; 1-888-ISP-PLDS; FAX (503) 681-3037; http://www.latticesemi.com
July 1997
18v10_03
1

GAL18V10-20LP相關(guān)型號(hào)PDF文件下載

掃碼下載APP，
一鍵連接廣大的電子世界。

在線(xiàn)人工客服

買(mǎi)家服務(wù)：
賣(mài)家服務(wù)：
技術(shù)客服：

0571-85317607

網(wǎng)站技術(shù)支持

13606545031

客服在線(xiàn)時(shí)間周一至周五
9:00-17:30

關(guān)注官方微信號(hào)，
第一時(shí)間獲取資訊。

建議反饋

聯(lián)系人：

聯(lián)系方式：

按住滑塊，拖拽到最右邊
>>
感謝您向阿庫(kù)提出的寶貴意見(jiàn)，您的參與是維庫(kù)提升服務(wù)的動(dòng)力！意見(jiàn)一經(jīng)采納，將有感恩紅包奉上哦！