12ns propagation delay provides the highest speed and lowest
DESCRIPTION
power combination PLD available in the market. The GAL16V8Z/
ZD is manufactured using Lattice Semiconductor's advanced zero
power E
2
CMOS process, which combines CMOS with Electrically
Erasable (E
2
) floating gate technology.
The GAL16V8Z uses Input Transition Detection (ITD) to put the
device in standby mode and is capable of emulating the full func-
tionality of the standard GAL16V8. The GAL16V8ZD utilizes a
dedicated power-down pin (DPP) to put the device in standby mode.
It has 15 inputs available to the AND array.
Unique test circuitry and reprogrammable cells allow complete AC,
DC, and functional testing during manufacture. As a result,
Lattice Semiconductor delivers 100% field programmability and
functionality of all GAL products. In addition, 100 erase/write cycles
and data retention in excess of 20 years are specified.
Pin Configuration
DIP/SOIC
PLCC
I/CLK
Vcc
I/O/Q
I/C LK
I
I
1
2
3
4
5
6
7
8
9
10
20
19
Vcc
I/ O/ Q
I/ O/ Q
I/ O/ Q
I/ O/ Q
I/ O/ Q
I
3
I/DPP
I
I
I
I
6
4
I
1
19
18
I/O/Q
I/O/Q
16
I/O/Q
I/O/Q
GAL
18
GAL16V8Z
GAL16V8ZD
Top View
9
I
GND
I/D P P
I
I
16V8Z
17
16V8ZD
16
15
14
13
12
11
I
I
I
GND
I/O/Q
I/O/Q
I/ O/ Q
I /O E
8
11
I/OE
I/O/Q
14
13
I/O/Q
I/O/Q
Copyright 漏 1997 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject
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