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GAL16V8D-20QJI Datasheet

  • GAL16V8D-20QJI

  • High Performance E2CMOS PLD Generic Array Logic

  • 22頁

  • LATTICE   LATTICE

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GAL16V8
High Performance E
2
CMOS PLD
Generic Array Logic鈩?/div>
Features
鈥?HIGH PERFORMANCE E
2
CMOS
廬
TECHNOLOGY
鈥?3.5 ns Maximum Propagation Delay
鈥?Fmax = 250 MHz
鈥?3.0 ns Maximum from Clock Input to Data Output
鈥?UltraMOS
廬
Advanced CMOS Technology
鈥?50% to 75% REDUCTION IN POWER FROM BIPOLAR
鈥?75mA Typ Icc on Low Power Device
鈥?45mA Typ Icc on Quarter Power Device
鈥?ACTIVE PULL-UPS ON ALL PINS
鈥?E CELL TECHNOLOGY
鈥?Reconfigurable Logic
鈥?Reprogrammable Cells
鈥?100% Tested/100% Yields
鈥?High Speed Electrical Erasure (<100ms)
鈥?20 Year Data Retention
鈥?EIGHT OUTPUT LOGIC MACROCELLS
鈥?Maximum Flexibility for Complex Logic Designs
鈥?Programmable Output Polarity
鈥?Also Emulates 20-pin PAL
廬
Devices with Full
Function/Fuse Map/Parametric Compatibility
鈥?PRELOAD AND POWER-ON RESET OF ALL REGISTERS
鈥?100% Functional Testability
鈥?APPLICATIONS INCLUDE:
鈥?DMA Control
鈥?State Machine Control
鈥?High Speed Graphics Processing
鈥?Standard Logic Speed Upgrade
鈥?ELECTRONIC SIGNATURE FOR IDENTIFICATION
I
8
I
OLMC
OE
Functional Block Diagram
I/CLK
CLK
8
I
8
I
OLMC
I/O/Q
OLMC
I/O/Q
PROGRAMMABLE
AND-ARRAY
(64 X 32)
8
OLMC
I/O/Q
2
I
8
OLMC
I/O/Q
I
8
OLMC
I/O/Q
I
8
OLMC
I/O/Q
I
8
OLMC
I/O/Q
I/O/Q
I/OE
Pin Configuration
PLCC
I
I
2
I
I
I
I
I
8
14
9
I
GND
11
I/OE I/O/Q
13
I/O/Q
6
4
I/CLK Vcc
20
18
I/O/Q
I/O/Q
16
I/O/Q
I/O/Q
I/O/Q
I/O/Q
Description
The GAL16V8, at 3.5 ns maximum propagation delay time, com-
bines a high performance CMOS process with Electrically Eras-
able (E
2
) floating gate technology to provide the highest speed
performance available in the PLD market. High speed erase times
(<100ms) allow the devices to be reprogrammed quickly and ef-
ficiently.
The generic architecture provides maximum design flexibility by
allowing the Output Logic Macrocell (OLMC) to be configured by
the user. An important subset of the many architecture configura-
tions possible with the GAL16V8 are the PAL architectures listed
in the table of the macrocell description section. GAL16V8 devices
are capable of emulating any of these PAL architectures with full
function/fuse map/parametric compatibility.
Unique test circuitry and reprogrammable cells allow complete AC,
DC, and functional testing during manufacture. As a result, Lattice
Semiconductor delivers 100% field programmability and function-
ality of all GAL products. In addition, 100 erase/write cycles and
data retention in excess of 20 years are specified.
DIP
I/CLK
I
I
I
I
I
5
15
1
20
Vcc
I/O/Q
I/O/Q
GAL16V8
Top View
GAL
16V8
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
SOIC
I/CLK
I
I
I
I
I
I
I
I
GND
10
5
1
20
Vcc
I/O/Q
I/O/Q
I/O/Q
I/O/Q
15
I/O/Q
I/O/Q
I/O/Q
I/O/Q
11
I/OE
I
I
I
GND
10
11
GAL
16V8
Top
View
I/OE
Copyright 漏 2001 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject
to change without notice.
LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A.
Tel. (503) 268-8000; 1-800-LATTICE; FAX (503) 268-8556; http://www.latticesemi.com
May 2001
16v8_08
1

GAL16V8D-20QJI 產(chǎn)品屬性

  • Lattice

  • GAL

  • 8

  • 50 MHz

  • 8

  • 20 ns

  • 5 V

  • 65 mA

  • + 85 C

  • - 40 C

  • PLCC-20

  • SMD/SMT

  • 8

  • Tube

  • 460

  • 5.5 V

  • 4.5 V

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