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GAL16LV8D-3LJN Datasheet

  • GAL16LV8D-3LJN

  • Low Voltage E2CMOS PLD Generic Array Logic⑩

  • 282.94KB

  • 22頁(yè)

  • LATTICE   LATTICE

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ree
Lead-F ge
P a c k a ns
Optio le!
b
Availa
GAL16LV8
Low Voltage E
2
CMOS PLD
Generic Array Logic鈩?/div>
Features
鈥?HIGH PERFORMANCE E
2
CMOS
廬
TECHNOLOGY
鈥?3.5 ns Maximum Propagation Delay
鈥?Fmax = 250 MHz
鈥?2.5 ns Maximum from Clock Input to Data Output
鈥?UltraMOS
廬
Advanced CMOS Technology
鈥?3.3V LOW VOLTAGE 16V8 ARCHITECTURE
鈥?JEDEC-Compatible 3.3V Interface Standard
鈥?5V Compatible Inputs
鈥?I/O Interfaces with Standard 5V TTL Devices
(GAL16LV8C)
鈥?ACTIVE PULL-UPS ON ALL PINS (GAL16LV8D Only)
鈥?E
2
CELL TECHNOLOGY
鈥?Reconfigurable Logic
鈥?Reprogrammable Cells
鈥?100% Tested/100% Yields
鈥?High Speed Electrical Erasure (<100ms)
鈥?20 Year Data Retention
鈥?EIGHT OUTPUT LOGIC MACROCELLS
鈥?Maximum Flexibility for Complex Logic Designs
鈥?Programmable Output Polarity
鈥?PRELOAD AND POWER-ON RESET OF ALL REGISTERS
鈥?100% Functional Testability
鈥?APPLICATIONS INCLUDE:
鈥?Glue Logic for 3.3V Systems
鈥?DMA Control
鈥?State Machine Control
鈥?High Speed Graphics Processing
鈥?Standard Logic Speed Upgrade
鈥?ELECTRONIC SIGNATURE FOR IDENTIFICATION
鈥?LEAD-FREE PACKAGE OPTIONS
Functional Block Diagram
I/CLK
CLK
8
I
8
I
OLMC
I/O/Q
OLMC
I/O/Q
PROGRAMMABLE
AND-ARRAY
(64 X 32)
8
OLMC
I/O/Q
I
8
OLMC
I/O/Q
I
8
OLMC
I/O/Q
I
8
OLMC
I/O/Q
I
8
I
8
I
OLMC
OE
OLMC
I/O/Q
I/O/Q
I/OE
Description
The GAL16LV8D, at 3.5 ns maximum propagation delay time,
provides the highest speed performance available in the PLD
market. The GAL16LV8C can interface with both 3.3V and 5V
signal levels. The GAL16LV8 is manufactured using Lattice
Semiconductor's advanced 3.3V E
2
CMOS process, which com-
bines CMOS with Electrically Erasable (E
2
) floating gate technology.
High speed erase times (<100ms) allow the devices to be repro-
grammed quickly and efficiently.
The 3.3V GAL16LV8 uses the same industry standard 16V8 archi-
tecture as its 5V counterpart and supports all architectural features
such as combinatorial or registered macrocell operations.
Unique test circuitry and reprogrammable cells allow complete AC,
DC, and functional testing during manufacture. As a result, Lattice
Semiconductor delivers 100% field programmability and function-
ality of all GAL products. In addition, 100 erase/write cycles and
data retention in excess of 20 years are specified.
Pin Configuration
PLCC
I
I
2
I
I
I
I
I
8
14
9
I
GND
11
I/OE I/O/Q
13
I/O/Q
6
4
I/CLK Vcc
20
18
I/O/Q
I/O/Q
I/O/Q
GAL16LV8
Top View
16
I/O/Q
I/O/Q
I/O/Q
Copyright 漏 2004 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject
to change without notice.
LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A.
Tel. (503) 268-8000; 1-800-LATTICE; FAX (503) 268-8556; http://www.latticesemi.com
August 2004
16lv8_05
1

GAL16LV8D-3LJN 產(chǎn)品屬性

  • 46

  • 集成電路 (IC)

  • 嵌入式 - CPLD（復(fù)雜可編程邏輯器件）

  • GAL®16LV8

  • EE PLD

  • 3.5ns

  • 3 V ~ 3.6 V

  • -

  • 8

  • -

  • -

  • 0°C ~ 75°C

  • 表面貼裝

  • 20-LCC（J 形引線(xiàn)）

  • 20-PLCC（9x9）

  • 管件

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