for matching against a 鈥榣ook-up鈥?/div>
table. Noise filtering is provided to improve the signal quality
prior to measurement.
NRZ
coded data streams for transmission, when
generated within a
碌Controller,
are loaded to the NRZ Tx
Data Buffer and output, in 8-bit bytes, through the Lowpass
Filter circuitry as sub-audio signals. CDCS turn-off tones can
be added to the data signals by switching the FX805 to the
CTCSS transmit mode at the appropriate time.
NRZ coding is produced by the
碌Controller
and translated
into sub-audio signals by the FX805.
Received NRZ data is filtered, detected and placed into
the NRZ Rx Data Register which is then available for transfer
one byte at a time, to the
碌Controller,
for decoding by
software. Clock extraction circuitry is provided on chip and
Rx and Tx baud rates are selectable.
Provision is made in both hardware and system software
allocations to address two FX805 Sub-Audio Signalling
Processors consecutively to achieve multi-mode, duplex
operation.
The FX805 has a powersaving function which may be
controlled by software or a dedicated (Wake) input.
The FX805 is a low-power, 5-volt CMOS integrated circuit
and is available in 24-pin DIL cerdip and 24-pin/lead plastic
SMD packages.
DPL is a registered trademark of Motorola Inc.
Publication D/805/3 July 1994