鈩?/div>
Microarchitecture
鈥?7-8 stage Intel
廬
Superpipelined
Technology
鈥?32-Entry Instruction Memory
Management Unit
鈥?32-Entry Data Memory Management
Unit
鈥?32 KByte, 32-way Set Associative
Instruction Cache
鈥?32 KByte, 32-way Set Associative Data
Cache
鈥?2 KByte, 2-way Set Associative
Mini-Data Cache
鈥?128-Entry Branch Target Buffer
鈥?8-Entry Write Buffer
鈥?4-Entry Fill and Pend Buffers
Intel
廬
Dynamic Voltage Management
鈥?Core Voltage Range: 0.95 V to 1.55 V
鈥?Internal Clock Scalable by Software up
to 733 MHz
鈥?Input Clock: 33-66 MHz
ARM* Version 5TE Compliant
Application-Code Compatible with
Intel
廬
StrongARM* SA-110
s
s
s
s
s
Power Management
鈥?Core Power is ~500mW at 600MHz
鈥?Core Voltage Operation Down to 0.95 V
鈥?Idle and Sleep Modes
Intel
廬
Media Processing Technology
鈥?Multiply-Accumulate Coprocessor
High Performance External Bus
鈥?64- or 32-Bit Data Interface
鈥?Optional ECC Protection
鈥?Frequency up to 100 MHz
鈥?Asynchronous to Processor Clock
Performance Monitoring Unit
鈥?Two 32-Bit Event Counters
鈥?One 32-Bit Clock Counter
鈥?Monitors Occurrence and Duration
Events
Debug Unit
鈥?Accessible through JTAG Port
鈥?Hardware Breakpoints
鈥?256-Entry Trace Buffer
August 2002
Reference Number: 273414-004