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FW32305 Datasheet

  • FW32305

  • 1394A PCI PHY/Link Open Host Controller Interface

  • 152頁

  • AGERE

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Data Sheet, Rev. 2
October 2001
FW323 05
1394A PCI PHY/Link Open Host Controller Interface
Features
s
s
1394a-2000 OHCI link and PHY core function in sin-
gle device:
鈥?Enables smaller, simpler, more efficient mother-
board and add-in card designs by replacing two
components with one
鈥?Enables lower system costs
鈥?Leverages proven 1394a-2000 PHY core design
鈥?Demonstrated compatibility with current
Microsoft
Windows
廬
drivers and common applications
鈥?Demonstrated interoperability with existing, as well
as older, 1394 consumer electronics and periph-
erals products
鈥?Feature-rich implementation for high performance
in common applications
鈥?Supports low-power system designs (CMOS
implementation, power management features)
鈥?Provides LPS, LKON, and CNA outputs to support
legacy power management implementations
OHCI:
鈥?Complies with OHCI 1.1 WHQL requirements
鈥?Complies with
Microsoft Windows
Logo Program
System and Device Requirements
鈥?Listed on
Windows
Hardware Compatibility List
s
http://www.microsoft.com/hcl/results.asp
鈥?Compatible with
Microsoft Windows
and
MacOS
廬
operating systems
鈥?4 Kbyte isochronous transmit FIFO
鈥?2 Kbyte asynchronous transmit FIFO
鈥?4 Kbyte isochronous receive FIFO
鈥?2 Kbyte asychronous receive FIFO
鈥?Dedicated asynchronous and isochronous
descriptor-based DMA engines
鈥?Eight isochronous transmit contexts
鈥?Eight isochronous receive contexts
鈥?Prefetches isochronous transmit data
鈥?Supports posted write transactions
1394a-2000 PHY core:
鈥?Compliant with
IEEE
廬
1394a-2000,
Standard for a
High Performance Serial Bus
(Supplement)
鈥?Provides three fully compliant cable ports, each
supporting 400 Mbits/s, 200 Mbits/s, and
100 Mbits/s traffic
鈥?Supports extended BIAS_HANDSHAKE time for
enhanced interoperability with camcorders
鈥?While unpowered and connected to the bus, will
not drive TPBIAS on a connected port even if
receiving incoming bias voltage on that port
鈥?Does not require external filter capacitor for PLL
鈥?Supports PHY core-link interface initialization and
reset
鈥?Supports link-on as a part of the internal
PHY core-link interface
鈥?25 MHz crystal oscillator and internal PLL provide
transmit/receive data at 100 Mbits/s, 200 Mbits/s,
and 400 Mbits/s, and internal link-layer controller
clock at 50 MHz
鈥?Interoperable across 1394 cable with 1394 phys-
ical layers (PHY core) using 5 V supplies
鈥?Node power-class information signaling for
system power management
鈥?Supports ack-accelerated arbitration and fly-by
concatenation
鈥?Supports arbitrated short bus reset to improve
utilization of the bus
鈥?Fully supports suspend/resume
鈥?Supports connection debounce
鈥?Supports multispeed packet concatenation
鈥?Supports PHY pinging and remote PHY access
packets
鈥?Reports cable power fail interrupt when voltage at
CPS pin falls below 7.5 V
鈥?Separate cable bias and driver termination voltage
supply for each port
Link:
鈥?Cycle master and isochronous resource manager
capable
鈥?Supports 1394a-2000 acceleration features
s

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