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FSTUD32450G Datasheet

  • FSTUD32450G

  • Configurable 4-Bit to 40-Bit Bus Switch with -2V Undershoot ...

  • 13頁

  • FAIRCHILD

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FSTUD32450 Configurable 4-Bit to 40-Bit Bus Switch with
鈭?V
Undershoot Protection and Selectable Level
Shifting
August 2001
Revised July 2002
FSTUD32450
Configurable 4-Bit to 40-Bit Bus Switch with
鈭?/div>
2V Undershoot Protection and Selectable Level Shifting
General Description
The Fairchild Universal Bus Switch FSTUD32450 provides
4-bit, 5-bit, 8-bit, 10-bit, 16-bit, 20-bit...40-bit of high-speed
CMOS TTL-compatible bus switching. The low On Resis-
tance of the switch allows inputs to be connected to out-
puts without adding propagation delay or generating
additional ground bounce noise.
The FSTUD32450 is designed to allow 鈥渃ustomer鈥?configu-
ration control of the enable connections. The device can be
organized as either a ten 4-bit, eight 5-bit, four 10-bit, two
20-bit or one 40-bit enabled bus switch. Also achievable
are 8-bit and 16-bit enabled configurations (see Functional
Description). The device's bit configuration is controlled
through select pin logic. (see Truth Table). When OE
x
is
LOW, Port A
x
is connected to Port B
x
. When OE
x
is HIGH,
the switch is OPEN.
The A and B Ports are protected against undershoot to
support an extended range to 2.0V below ground.
Fairchild's integrated Undershoot Hardened Circuit
(UHC
錚?/div>
) senses undershoot at the I/O, and responds by
preventing voltage differentials from developing and turn-
ing the switch on.
Another innovative device feature is the addition of a level
shifting select pin, 鈥淪
2
and S
5
鈥? When S
2
and S
5
are LOW,
the device behaves as a standard N-MOS switch. When S
2
and S
5
are HIGH, a diode to V
CC
is integrated into the cir-
cuit allowing for level shifting between 5V inputs and 3.3V
outputs.
Features
I
Undershoot protected to
鈭?/div>
2V (A and B Ports)
I
Voltage level shifting
I
4
鈩?/div>
switch connection between two ports
I
Minimal propagation delay through the switch
I
Low l
CC
I
Zero bounce in flow-through mode
I
Control inputs compatible with TTL level
I
See Applications Notes AN-5008 and AN-5021 for UHC
details
I
Packaged in plastic Fine-Pitch Ball Grid Array (FBGA)
Applications Note
Select pins S
0
, S
1
, S
2
, S
3
, S
4
and S
5
are intended to be
used as static user configurable control pins. The AC per-
formance of these pins has not been characterized or
tested. Switching of these select pins during system opera-
tion may temporarily disrupt output logic states and/or
enable pin controls.
40-bit configuration can be achieved by connecting the
OE
1
and the OE
6
pins to together.
Ordering Code:
Order Number
FSTUD32450G
(Note 1)(Note 2)
Package Number
BGA114A
Package Description
114-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide
Note 1:
Ordering code 鈥淕鈥?indicates Trays.
Note 2:
Devices also available in Tape and Reel. Specify by appending the suffix letter 鈥淴鈥?to the ordering code.
UHC錚?is a trademark of Fairchild Semiconductor Corporation.
漏 2002 Fairchild Semiconductor Corporation
DS500447
www.fairchildsemi.com

FSTUD32450G 產品屬性

  • Fairchild Semiconductor

  • 數(shù)字總線開關 IC

  • 0.25 ns at 4 V to 5.5 V

  • + 85 C

  • - 40 C

  • BGA-114

  • Tray

  • FST

  • SMD/SMT

  • 35 Ohms

  • 240

  • 5.5 V

  • 4 V

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