鈩?/div>
Series Resistors in Outputs
General Description
The Fairchild Universal Bus Switch FSTUD162450 pro-
vides 4-bit, 5-bit, 8-bit, 10-bit, 16-bit, 20-bit of high-speed
CMOS TTL-compatible bus switching. The low On Resis-
tance of the switch allows inputs to be connected to out-
puts without adding propagation delay or generating
additional ground bounce noise.
The FSTUD162450 is designed to allow 鈥渃ustomer鈥?config-
uration control of the enable connections. The device can
be organized as either a five 4-bit, four 5-bit, two 10-bit or
one 20-bit bus switch. Also available are 8-bit and 16-bit
enabled configurations (see Functional Description). The
device's bit configuration is controlled through select pin
logic. (see Truth Table). When OE
x
is LOW, Port A
x
is con-
nected to Port B
x
. When OE
x
is HIGH, the switch is OPEN.
The A and B Ports are protected against undershoot to
support an extended range to 2.0V below ground.
Fairchild's integrated Undershoot Hardened Circuit
(UHC
錚?/div>
) senses undershoot at the I/O and responds by
preventing voltage differentials from developing and turn-
ing the switch on.
Another innovative device feature is the addition of a level
shifting select pin, 鈥淪
2
鈥? When S
2
is LOW, the device
behaves as a standard N-MOS switch. When S
2
is HIGH, a
diode to V
CC
is integrated into the circuit allowing for level
shifting between 5V inputs and 3.3V outputs.
Features
s
Undershoot protected to
鈭?/div>
2V (A and B Ports)
s
Voltage level shifting
s
25
鈩?/div>
switch connection between two ports
s
Minimal propagation delay through the switch
s
Low l
CC
s
Zero bounce in flow-through mode
s
Control inputs compatible with TTL level
s
See Applications Notes AN-5008 and AN-5021
for UHC details
s
Also packaged in plastic Fine-Pitch Ball Grid Array
(FBGA) (Preliminary)
Applications Note
Select pins S
0
, S
1
, S
2
are intended to be used as static
user configurable control pins. The AC performance of
these pins has not been characterized or tested. Switching
of these select pins during system operation may tempo-
rarily disrupt output logic states and/or enable pin controls.
Ordering Code:
Order Number
FSTUD162450GX
(Note 1)
FSTUD162450MTD
Package Number
BGA54A
Preliminary
MTD56
Package Description
54-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide
[Tape and Reel]
56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter 鈥淴鈥?to the ordering code.
Note 1:
BGA package available in Tape and Reel only.
UHC錚?is a trademark of Fairchild Semiconductor Corporation.
漏 2001 Fairchild Semiconductor Corporation
DS500469
www.fairchildsemi.com
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