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FSTD16450MTD Datasheet

  • FSTD16450MTD

  • Configurable 4-Bit to 20-Bit Bus Switch with Selectable Leve...

  • 11頁(yè)

  • FAIRCHILD

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FSTD16450 Configurable 4-Bit to 20-Bit Bus Switch with Selectable Level Shifting
January 2001
Revised August 2001
FSTD16450
Configurable 4-Bit to 20-Bit Bus Switch
with Selectable Level Shifting
General Description
The Fairchild Universal Bus Switch FSTD16450 provides
4-bit, 5-bit, 8-bit, 10-bit, 16-bit, 20-bit of high-speed CMOS
TTL-compatible bus switching. The low on resistance of
the switch allows inputs to be connected to outputs without
adding propagation delay or generating additional ground
bounce noise.
The FSTD16450 is designed to allow 鈥渃ustomer鈥?configura-
tion control of the enable connections. The device is orga-
nized as either a 4-bit, 5-bit, 10-bit or 20-bit bus switch. 8-
bit and 16-bit configurations are also achievable (see Func-
tional Description). The device's bit configuration is chosen
through select pin logic. (see Truth Table). When OE
x
is
LOW, Port A
x
is connected to Port B
x
. When OE
x
is HIGH,
the switch is OPEN.
Another key device feature is the addition of a level shifting
select pin, 鈥淪
2
鈥? When S
2
is LOW, the device behaves as a
standard N-MOS switch. When S
2
is HIGH, a diode to V
CC
is integrated into the circuit allowing for level shifting
between 5V inputs and 3.3V outputs.
Features
s
4
鈩?/div>
switch connection between two ports
s
Voltage level shifting
s
Minimal propagation delay through the switch
s
Low l
CC
s
Zero bounce in flow-through mode
s
Control inputs compatible with TTL level
s
Also packaged in plastic Fine-Pitch Ball Grid Array
(FBGA) (Preliminary)
Applications Note
Select pins S
0
, S
1
, S
2
are intended to be used as static
user configurable control pins. The AC performance of
these pins has not been characterized or tested. Switching
of these select pins during system operation may tempo-
rarily disrupt output logic states and/or enable pin controls.
Ordering Code:
Order Number
FSTD16450GX
(Note 1)
FSTD16450MTD
Package Number
BGA54A
(Preliminary)
MTD56
Package Description
54-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide
[Tape and Reel]
56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter 鈥淴鈥?to the ordering code.
Note 1:
BGA package available in Tape and Reel only.
UHC錚?is a trademark of Fairchild Semiconductor Corporation.
漏 2001 Fairchild Semiconductor Corporation
DS500438
www.fairchildsemi.com

FSTD16450MTD 產(chǎn)品屬性

  • Fairchild Semiconductor

  • 數(shù)字總線開關(guān) IC

  • Quint

  • 0.25 ns at 4 V to 5.5 V

  • + 85 C

  • - 40 C

  • TSSOP-56

  • Tube

  • FST

  • SMD/SMT

  • 35 Ohms

  • 34

  • 7 V

  • 0.5 V

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