鈩?/div>
@ V
GS
= 10 V
鈥?Low gate charge ( typical 16 nC )
鈥?Low Crss ( typical 7 pF)
鈥?Fast switching
鈥?100 % avalanche tested
鈥?Improved dv/dt capability
廬
Description
These N-Channel enhancement mode power field effect
transistors are produced using Fairchild鈥檚 proprietary, planar
stripe, DMOS technology.
This advanced technology has been especially tailored to
minimize on-state resistance, provide superior switching
performance, and withstand high energy pulse in the avalanche
and commutation mode. These devices are well suited for high
efficiency switched mode power supplies, active power factor
correction, electronic lamp ballasts based on half bridge
topology.
D
D
!
鈼?/div>
鈼€
鈻?/div>
鈼?/div>
鈼?/div>
G
S
D-PAK
FQD Series
G
!
!
S
Absolute Maximum Ratings
Symbol
V
DSS
I
D
I
DM
V
GSS
E
AS
I
AR
E
AR
dv/dt
P
D
T
J
, T
STG
T
L
Drain Current
Drain Current
Parameter
Drain-Source Voltage
- Continuous (T
C
= 25擄C)
- Continuous (T
C
= 100擄C)
- Pulsed
(Note 1)
(Note 2)
(Note 1)
(Note 1)
(Note 3)
Gate-Source Voltage
Single Pulsed Avalanche Energy
Avalanche Current
Repetitive Avalanche Energy
Peak Diode Recovery dv/dt
Power Dissipation (T
C
= 25擄C)
- Derate above 25擄C
Operating and Storage Temperature Range
Maximum lead temperature for soldering purposes,
1/8" from case for 5 seconds
FQD6N60C
600
4
2.4
16
鹵
30
300
4.0
8.0
4.5
80
0.78
-55 to +150
300
Units
V
A
A
A
V
mJ
A
mJ
V/ns
W
W/擄C
擄C
擄C
Thermal Characteristics
Symbol
R
胃JC
R
胃JA
R
胃JA
Parameter
Thermal Resistance, Junction-to-Case
Thermal Resistance, Junction-to-Ambient *
Thermal Resistance, Junction-to-Ambient
Typ
--
--
--
Max
1.56
50
110
Units
擄C/W
擄C/W
擄C/W
* When mounted on the minimum pad size recommended (PCB Mount)
漏2005 Fairchild Semiconductor Corporation
1
www.fairchildsemi.com
FQD6N60C Rev. A
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