鈥?/div>
108/140 Ms/s conversion rate
RGB and YP
B
P
R
clamps
444 and 422 output timing
Adjustable Gain and offset
Internal Reference Voltage
I
2
C/SMBus compatible Serial Port
100-pin package
The ADC sampling clock can be derived from either an
external source or from incoming horizontal sync using the
internal PLL. Setup and control is via registers accessible
through an SMBus/I
2
C compatible serial port.
Input amplitude range is 500鈥?000mV with either DC or AC
coupling. AC coupled inputs can be clamped to program-
mable midpoint/bottom levels or to external reference levels
using either internal or externally generated clamp timing.
Common to the three channels are clamp pulses, a bandgap
reference voltage and clocks derived from the HSYNC PLL
or an external clock source. Digital data output levels are
2.5鈥?.3V CMOS compliant.
Power is derived from a single +3.3 Volt power supply. Package
is a low cost 100-lead MQFP. Performance speci鏗乧ations are
guaranteed over 0擄C to 70擄C.
Product Number
FMS9875KAC100
FMS9875KAC140
Speed
108 Ms/s
140 Ms/s
Applications
鈥?YP
B
P
R
Digitizers
鈥?Projectors
鈥?TV sets
Description
As a fully integrated graphics interface, the FMS9875 can
digitize RGB or YP
B
P
R
video signals at resolutions up to
1280 x 1024 with 75 Hz refresh rate. Compatible video
formats include NTSC-601, PAL-601, SMPTE 293M,
SMPTE 296M and SMPTE 274M.
Block Diagram
GY
IN
GY
REF
Bottom
Clamp
Gain &
Offset
A/D
DGY
7-0
BP
IN
BP
REF
Bottom/
Midpoint
Clamp
Gain &
Offset
A/D
444/422
DBP
7-0
RP
IN
RP
REF
Bottom/
Midpoint
Clamp
Gain &
Offset
ICLAMP
A/D
444/422
DRP
7-0
VREFIN
CLAMP
INVSCK
XCK
HSIN
COAST
LPF
SDA
SCL
A
0
A
1
PWRDN
HS
PLL
PXCK
SCK
Reference
VREFOUT
Timing
Generator
ICLAMP
DCK
DCK
HSOUT
Control
ACS
IN
SYNC
Stripper
DCS
OUT
REV. 1.2.15 1/14/02