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FM27C010N90 Datasheet

  • FM27C010N90

  • 1,048,576-Bit 128K x 8 High Performance CMOS EPROM

  • 111.14KB

  • 10頁

  • FAIRCHILD

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FM27C010 1,048,576-Bit (128K x 8) High Performance CMOS EPROM
January 2000
FM27C010
1,048,576-Bit (128K x 8) High Performance
CMOS EPROM
General Description
The FM27C010 is a high performance, 1,048,576-bit Electrically
Programmable UV Erasable Read Only Memory. It is organized
as 128K-words of 8 bits each. Its pin-compatibility with byte-wide
JEDEC EPROMs enables upgrades through 8 Mbit EPROMs.
The 鈥淒on鈥檛 Care鈥?feature during read operations allows memory
expansions from 1M to 8M bits with no printed circuit board
changes.
The FM27C010 can directly replace lower density 28-pin EPROMs
by adding an A16 address line and V
CC
jumper. During the normal
read operation PGM and V
PP
are in a 鈥淒on鈥檛 Care鈥?state which
allows higher order addresses, such as A17, A18, and A19 to be
connected without affecting the normal read operation. This
allows memory upgrades to 8M bits without hardware changes.
The FM27C010 is also offered in a 32-pin plastic DIP with the
same upgrade path.
The FM27C010 provides microprocessor-based systems exten-
sive storage capacity for large portions of operating system and
application software. Its 70 ns access time provides no-wait-state
operation with high-performance CPUs. The FM27C010 offers a
single chip solution for the code storage requirements of 100%
firmware-based equipment. Frequently-used software routines
are quickly executed from EPROM storage, greatly enhancing
system utility.
The FM27C010 is manufactured using Fairchild鈥檚 advanced CMOS
AMG鈩?EPROM technology.
The FM27C010 is one member of a high density EPROM Family
which range in densities up to 4 Megabit.
Features
I
High performance CMOS
鈥?70 ns access time
I
Fast turn-off for microprocessor compatibility
I
Simplified upgrade path
鈥?V
PP
and PGM are 鈥淒on鈥檛 Care鈥?during normal read
operation
I
Manufacturers identification code
I
Fast programming
I
JEDEC standard pin configurations
鈥?32-pin PDIP package
鈥?32-pin PLCC package
鈥?32-pin CERDIP package
Block Diagram
V
CC
GND
V
PP
OE
CE
PGM
Output Enable,
Chip Enable, and
Program Logic
Data Outputs O
0
- O
7
Output
Buffers
Y Decoder
..
1,048,576-Bit
Cell Matrix
A
0
- A
16
Address
Inputs
.......
X Decoder
DS800032-1
漏 2000 Fairchild Semiconductor Corporation
FM27C010
1
www.fairchildsemi.com

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