FIN1049 LVDS Dual Line Driver with Dual Line Receiver
March 2003
Revised March 2003
FIN1049
LVDS Dual Line Driver with Dual Line Receiver
General Description
This dual Driver-Receiver is designed for high speed inter-
connects utilizing Low Voltage Differential Signaling
(LVDS) technology. The Driver accepts LVTTL inputs and
translates them to LVDS outputs. The Receiver accepts
LVDS inputs and translates them to LVTTL outputs. The
LVDS levels have a typical differential output swing of
350mV which provide for low EMI at ultra low power dissi-
pation even at high frequencies. The FIN1049 can accept
LVPECL inputs for translating from LVPECL to LVDS. The
En and Enb inputs are ANDed together to enable/disable
the outputs. The enables are common to all four outputs. A
single line driver and single line receiver function is also
available in the FIN1019.
Features
s
Greater than 400 Mbps data rate
s
3.3V power supply operation
s
Low power dissipation
s
Fail safe protection for open-circuit conditions
s
Meets or exceeds the TIA/EIA-644-A LVDS standard
s
16-pin TSSOP package saves space
s
Flow-through pinout simplifies PCB layout
s
Enable/Disable for all outputs
s
Industrial operating temperature range:
鈭?/div>
40
擄
C to
+
85
擄
C
Ordering Code:
Order Number
FIN1049MTC
Package Number
MTC16
Package Description
16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Device also available in Tape and Reel. Specify by appending suffix letter 鈥淴鈥?to the ordering code.
Pin Descriptions
Pin Name
R
IN1+
, R
IN2+
R
IN1鈭?/div>
, R
IN2鈭?/div>
Description
Non-Inverting LVDS Inputs
Inverting LVDS Inputs
Connection Diagram
D
OUT1+
, D
OUT2+
Non-Inverting Driver Outputs
D
OUT1鈭?/div>
, D
OUT2鈭?/div>
Inverting Driver Outputs
EN, ENb
R
OUT1
, R
OUT2
D
IN2
, D
IN2
V
CC
GND
Driver Enable Pins for All Outputs
LVTTL Output Pins for R
OUT1
and R
OUT2
LVTTL Input Pins for D
IN1
and D
IN2
Power Supply (3.3V)
Ground
漏 2003 Fairchild Semiconductor Corporation
DS500846
www.fairchildsemi.com
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