FIN1017 3.3V LVDS 1-Bit High Speed Differential Driver
April 2001
Revised April 2002
FIN1017
3.3V LVDS 1-Bit High Speed Differential Driver
General Description
This single driver is designed for high speed interconnects
utilizing Low Voltage Differential Signaling (LVDS) technol-
ogy. The driver translates LVTTL signal levels to LVDS lev-
els with a typical differential output swing of 350 mV which
provides low EMI at ultra low power dissipation even at
high frequencies. This device is ideal for high speed trans-
fer of clock or data.
The FIN1017 can be paired with its companion receiver,
the FIN1018, or with any other LVDS receiver.
Features
s
Greater than 600Mbs data rate
s
3.3V power supply operation
s
0.5ns maximum differential pulse skew
s
1.5ns maximum propagation delay
s
Low power dissipation
s
Power-Off protection
s
Meets or exceeds the TIA/EIA-644 LVDS standard
s
Flow-through pinout simplifies PCB layout
s
8-Lead SOIC and US8 packages save space
Ordering Code:
Order Number
FIN1017M
FIN1017MX
FIN1017K8X
Package Number
M08A
M08A
MAB08A
Package Description
8-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
[TUBE]
8-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
[TAPE and REEL]
8-Lead US8, JEDEC MO-187, Variation CA 3.1mm Wide
[TAPE and REEL]
Connection Diagrams
8-Lead SOIC
Pin Assignment for US-8 Package
Note:
Ground pins 4 and 5 for optimum operation.
TOP VIEW
Pin Descriptions
Pin Name
D
IN
D
OUT+
D
OUT鈭?/div>
V
CC
GND
NC
Description
LVTTL Data Input
Non-inverting Driver Output
Inverting Driver Output
Power Supply
Ground
No Connect
Function Table
Input
D
IN
L
H
OPEN
H
=
HIGH Logic Level
Outputs
D
OUT+
L
H
L
L
=
LOW Logic Level
D
OUT鈭?/div>
H
L
H
X
=
Don鈥檛 Care
漏 2002 Fairchild Semiconductor Corporation
DS500500
www.fairchildsemi.com
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