FIN1001 3.3V LVDS 1-Bit High Speed Differential Driver
December 2001
Revised January 2002
FIN1001
3.3V LVDS 1-Bit High Speed Differential Driver
General Description
This single driver is designed for high speed interconnects
utilizing Low Voltage Differential Signaling (LVDS) technol-
ogy. The driver translates LVTTL signal levels to LVDS lev-
els with a typical differential output swing of 350 mV which
provides low EMI at ultra low power dissipation even at
high frequencies. This device is ideal for high speed trans-
fer of clock or data.
The FIN1001 can be paired with its companion receiver,
the FIN1002, or with any other LVDS receiver.
Features
I
Greater than 600Mbs data rate
I
3.3V power supply operation
I
0.5ns maximum differential pulse skew
I
1.5ns maximum propagation delay
I
Low power dissipation
I
Power-Off protection
I
Meets or exceeds the TIA/EIA-644 LVDS standard
I
Flow-through pinout simplifies PCB layout
I
5-Lead SOT23 package saves space
Ordering Code:
Order Number
FIN1001M5
FIN1001M5X
Package Number
MA05B
MA05B
Package Description
5-Lead SOT23, JEDEC MO-178, 1.6mm [250 Units on Tape and Reel]
5-Lead SOT23, JEDEC MO-178, 1.6mm [3000 Units on Tape and Reel]
Pin Descriptions
Pin Name
D
IN
D
OUT+
D
OUT鈭?/div>
V
CC
GND
NC
Description
LVTTL Data Input
Non-inverting LVDS Driver Output
Inverting LVDS Driver Output
Power Supply
Ground
No Connect
Connection Diagram
Pin Assignment for SOT23
Function Table
Input
D
IN
L
H
H
=
HIGH Logic Level
Outputs
D
OUT+
L
H
L
=
LOW Logic Level
D
OUT鈭?/div>
H
L
(Top View)
漏 2002 Fairchild Semiconductor Corporation
DS500721
www.fairchildsemi.com
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