July 1997
FDC6301N
Dual N-Channel , Digital FET
General Description
These dual N-Channel logic level enhancement mode field
effect transistors are produced using Fairchild 's proprietary,
high cell density, DMOS technology. This very high density
process is especially tailored to minimize on-state resistance.
This device has been designed especially for low voltage
applications as a replacement for digital transistors. Since bias
resistors are not required, these N-Channel FET's can replace
several digital transistors, with a variety of bias resistors.
Features
25 V, 0.22 A continuous, 0.5 A Peak.
R
DS(ON)
= 5
鈩?/div>
@ V
GS
= 2.7 V
R
DS(ON)
= 4
鈩?/div>
@ V
GS
= 4.5 V.
Very low level gate drive requirements allowing direct
operation in 3V circuits. V
GS(th)
< 1.5V.
Gate-Source Zener for ESD ruggedness.
>6kV Human Body Model.
SOT-23
SuperSOT -6
Mark: .301
TM
SuperSOT -8
TM
SO-8
SOT-223
SOIC-16
INVERTER APPLICATION
Vcc
4
3
D
OUT
5
6
2
IN
G
S
GND
1
Absolute Maximum Ratings
Symbol
V
DSS
, V
CC
V
GSS
, V
IN
I
D
, I
OUT
P
D
T
J
,T
STG
ESD
Parameter
T
A
= 25
o
C unless other wise noted
FDC6301N
25
8
Units
V
V
A
Drain-Source Voltage, Power Supply Voltage
Gate-Source Voltage, V
IN
Drain/Output Current
- Continuous
- Pulsed
Maximum Power Dissipation
(Note 1a)
(Note 1b)
0.22
0.5
0.9
0.7
-55 to 150
6.0
W
Operating and Storage Temperature Range
Electrostatic Discharge Rating MIL-STD-883D
Human Body Model (100pf / 1500 Ohm)
擄C
kV
THERMAL CHARACTERISTICS
R
胃JA
R
胃JC
Thermal Resistance, Junction-to-Ambient
Thermal Resistance, Junction-to-Case
(Note 1a)
(Note 1)
140
60
擄C/W
擄C/W
FDC6301N Rev.C
漏 1997 Fairchild Semiconductor Corporation
1
2
3
4
