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FAN1654 Datasheet

  • FAN1654

  • 1.5A LDO, DDR Bus Termination Regulator

  • 7頁

  • FAIRCHILD

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www.fairchildsemi.com
FAN1654
1.5A LDO, DDR Bus Termination Regulator
Features
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Sinks and sources 1A continuous, 1.5A peak
-40擄C to +125擄C Operating Range
Load regulation: (VDDQ/2) 鹵 40mV
5mA VREF buffer tracks VTT
On-chip thermal limiting
Power-enhanced eTSSOP鈩?16 package
Low Current Shutdown Mode
Output Short Circuit Protection
Description
The FAN1654 is a low-cost bi-directional LDO specifically
designed for terminating DDR memory bus. It can both sink
and source up to 1A continuous, 1.5A peak, providing
enough current for most DDR applications. Load regulation
meets the JEDEC spec, VTT = (VDDQ/2) 鹵 40mV.
The FAN1654 includes a buffered reference voltage capable
of supplying up to 5mA current. On-chip thermal limiting
provides protection against a combination of power overload
and ambient temperature that would create an excessive
junction temperature. A shutdown input puts the FAN1654
into a low power mode for laptop computer applications.
The FAN1654 regulator is available in a power-enhanced
eTSSOP鈩?16 package, and the standard SOIC-14
Applications
鈥?DDR terminators
Block Diagram
VDDQ
200k
-
VREFOUT
VREFIN
+
VTTFORCE
+
VTTFORCE
-
200k
VTTSENSE
FAN1655
VSSQ
VSS
VSS
VSS
VDD
VDD
VDD
SHDN
REV. 1.0.5 4/17/02

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