鈥?/div>
2.85V Operation
HCMOS Output
Standby Function
Tape and Reel
(2,000 pcs. STD)
OPTIONS
鈥?5.0V (F550L) Version Available
5 .0 鹵 0 .2
鈥?PART NUMbER SElEcTION
Learn More - Internet Required
Part Number
661-Frequency-xxxxx
662-Frequency-xxxxx
663-Frequency-xxxxx
664-Frequency-xxxxx
499-Frequency-xxxxx
659-Frequency-xxxxx
520-Frequency-xxxxx
Model
Number
F520L
F520LR
F525L
F525LR
F526L
F526LR
F528L
Frequency
Stability
1
鹵100PPM
鹵100PPM
鹵50PPM
鹵50PPM
鹵25PPM
鹵25PPM*
鹵20PPM*
Operating
Temperature (潞C)
-10 ~ +70
-40 ~ +85
-10 ~ +70
-40 ~ +85
-10 ~ +70
-40 ~ +85
-10 ~ +70
Frequency
Range (MHz)
1.544 ~ 80.000
1.544 ~ 80.000
1.544 ~ 80.000
1.544 ~ 80.000
1.544 ~ 80.000
1.544 ~ 80.000
1.544 ~ 80.000
3 .2 鹵 0 .2
1 .3 M ax
鈥?ElEcTRIcAl cHARAcTERISTIcS
PARAMETERS
Frequency Range (F
o
)
Storage Temperature Range (T
stg
)
Supply Voltage
(V
dd
)
Input Current
(I
dd
)
1.544 ~ 32.000 MHz
32.000+ ~ 50.000 MHz
50.000+ ~ 80.000 MHz
Output Symmetry (50% V
dd
)
Rise Time (10% ~ 90% V
dd
) (T
r
)
Fall Time (90% ~ 10% V
dd
) (T
f
)
Output Voltage
(V
ol
)
(V
oh
)
Output Current
(I
ol
)
(I
oh
)
Output Load
(HCMOS)
Standby Current
Start-up Time
(T
s
)
Output Disable Time
2
Output Enable Time
2
1
2 .5 4鹵0.1
MAX
(unless otherwise noted)
1.544 ~ 80.000 MHz
-55潞C ~ +125潞C
2.85V 鹵 5%
12mA
20mA
40mA
45% ~ 55%
5nS
5nS
10% V
dd
90% V
dd
Min
4mA Min
-4mA Min
15pF
10碌A(chǔ)
10mS
150nS
10mS
1 .2
One center castellation,
two offset from center castellations,
or no castellations may be present
on 3.2mm sides.
1 .0
Recommended
Solder Pad Layout
2.54
1.29
2.25
Inclusive of 25潞C tolerance, operating temperature range, input voltage change, load change, aging,
shock, and vibration. *Excludes Shock/Vibration
2
An internal pullup resistor from pin 1 to pin 4 allows active output if pin 1 is left open.
Note: A 0.01碌F bypass capacitor should be placed between V
dd
(Pin 4) and GND (Pin 2) to
minimize power supply line noise.
All specifications subject to change without notice.
1.24
All dimensions are in millimeters.
Pin Connections
# 1 E /D
#2 G ND
# 3 O u tp u t
#4 V
DD
鈥?ENAblE / DISAblE FUNcTION
INH (Pin 1)
OUTPUT (Pin 3)
OPEN
2
ACTIVE
'1' Level V
ih
鈮?/div>
70% V
dd
ACTIVE
'0' Level V
il
鈮?/div>
30% V
dd
High Z
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