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EBD11UD8ADDA-7B Datasheet

  • EBD11UD8ADDA-7B

  • 1GB DDR SDRAM SO-DIMM (128M words x64 bits, 2 Ranks)

  • 205.09KB

  • 19頁

  • ELPIDA

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DATA SHEET
1GB DDR SDRAM SO-DIMM
EBD11UD8ADDA
(128M words
脳
64 bits, 2 Ranks)
Description
The EBD11UD8ADDA is 128M words
脳
64 bits, 2
ranks Double Data Rate (DDR) SDRAM Small Outline
Dual In-line Memory Module, mounting 16 pieces of
512M bits DDR SDRAM sealed in TCP package. Read
and write operations are performed at the cross points
of the CK and the /CK. This high-speed data transfer
is realized by the 2 bits prefetch-pipelined architecture.
Data strobe (DQS) both for read and write are available
for high speed and reliable data bus design. By setting
extended mode register, the on-chip Delay Locked
Loop (DLL) can be set enable or disable. This module
provides high density mounting without utilizing surface
mount technology. Decoupling capacitors are mounted
beside each TCP on the module board.
Note: Do not push the cover or drop the modules in
order to avoid mechanical defects, which may
result in electrical defects.
Features
鈥?/div>
200-pin socket type small outline dual in line memory
module (SO-DIMM)
錚?/div>
PCB height: 31.75mm
錚?/div>
Lead pitch: 0.6mm
鈥?/div>
2.5V power supply
鈥?/div>
Data rate: 333Mbps/266Mbps (max.)
鈥?/div>
2.5 V (SSTL_2 compatible) I/O
鈥?/div>
Double Data Rate architecture; two data transfers per
clock cycle
鈥?/div>
Bi-directional, data strobe (DQS) is transmitted
/received with data, to be used in capturing data at
the receiver
鈥?/div>
Data inputs, outputs and DM are synchronized with
DQS
鈥?/div>
4 internal banks for concurrent operation
(Components)
鈥?/div>
DQS is edge aligned with data for READs; center
aligned with data for WRITEs
鈥?/div>
Differential clock inputs (CK and /CK)
鈥?/div>
DLL aligns DQ and DQS transitions with CK
transitions
鈥?/div>
Commands entered on each positive CK edge; data
referenced to both edges of DQS
鈥?/div>
Data mask (DM) for write data
鈥?/div>
Auto precharge option for each burst access
鈥?/div>
Programmable burst length: 2, 4, 8
鈥?/div>
Programmable /CAS latency (CL): 2, 2.5
鈥?/div>
Refresh cycles: (8192 refresh cycles /64ms)
錚?/div>
7.8碌s maximum average periodic refresh interval
鈥?/div>
2 variations of refresh
錚?/div>
Auto refresh
錚?/div>
Self refresh
Document No. E0431E20 (Ver. 2.0)
Date Published April 2004 (K) Japan
URL: http://www.elpida.com
錚〦lpida
Memory, Inc. 2003-2004

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