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EBD10RD4ADFA-6B Datasheet

  • EBD10RD4ADFA-6B

  • 1GB Registered DDR SDRAM DIMM (128M words x72 bits, 1 Rank)

  • 218.75KB

  • 19頁

  • ELPIDA

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DATA SHEET
1GB Registered DDR SDRAM DIMM
EBD10RD4ADFA
(128M words
脳
72 bits, 1 Rank)
Description
The EBD10RD4ADFA is 128M words
脳
72 bits, 1 rank
Double Data Rate (DDR) SDRAM registered module,
mounting 18 pieces of 512M bits DDR SDRAM sealed
in TSOP package. Read and write operations are
performed at the cross points of the CK and the /CK.
This high-speed data transfer is realized by the 2-bit
prefetch-pipelined architecture. Data strobe (DQS)
both for read and write are available for high speed and
reliable data bus design. By setting extended mode
register, the on-chip Delay Locked Loop (DLL) can be
set enable or disable. This module provides high
density mounting without utilizing surface mount
technology.
Decoupling capacitors are mounted
beside each TSOP on the module board.
Features
鈥?/div>
184-pin socket type dual in line memory module
(DIMM)
錚?/div>
PCB height: 30.48mm
錚?/div>
Lead pitch: 1.27mm
鈥?/div>
2.5V power supply
鈥?/div>
Data rate: 333Mbps/266Mbps (max.)
鈥?/div>
2.5 V (SSTL_2 compatible) I/O
鈥?/div>
Double Data Rate architecture; two data transfers per
clock cycle
鈥?/div>
Bi-directional, data strobe (DQS) is transmitted
/received with data, to be used in capturing data at
the receiver
鈥?/div>
Data inputs and outputs are synchronized with DQS
鈥?/div>
4 internal banks for concurrent operation
(Component)
鈥?/div>
DQS is edge aligned with data for READs; center
aligned with data for WRITEs
鈥?/div>
Differential clock inputs (CK and /CK)
鈥?/div>
DLL aligns DQ and DQS transitions with CK
transitions
鈥?/div>
Commands entered on each positive CK edge; data
referenced to both edges of DQS
鈥?/div>
Auto precharge option for each burst access
鈥?/div>
Programmable burst length: 2, 4, 8
鈥?/div>
Programmable /CAS latency (CL): 2, 2.5
鈥?/div>
Refresh cycles: (8192 refresh cycles /64ms)
錚?/div>
7.8碌s maximum average periodic refresh interval
鈥?/div>
2 variations of refresh
錚?/div>
Auto refresh
錚?/div>
Self refresh
鈥?/div>
1 piece of PLL clock driver, 2 pieces of register driver
and 1 piece of serial EEPROM (2k bits) for Presence
Detect (SPD) on PCB.
Document No. E0430E20 (Ver. 2.0)
Date Published January 2004 (K) Japan
URL: http://www.elpida.com
錚〦lpida
Memory,Inc. 2003-2004

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