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E28F001BX-B120 Datasheet

  • E28F001BX-B120

  • 1-MBIT (128K x 8) BOOT BLOCK FLASH MEMORY

  • 33頁(yè)

  • INTEL   INTEL

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1-MBIT (128K x 8)
BOOT BLOCK FLASH MEMORY
28F001BX-T 28F001BX-B 28F001BN-T 28F001BN-B
Y
High-Integration Blocked Architecture
One 8 KB Boot Block w Lock Out
Two 4 KB Parameter Blocks
One 112 KB Main Block
100 000 Erase Program Cycles Per
Block
Simplified Program and Erase
Automated Algorithms via On-Chip
Write State Machine (WSM)
SRAM-Compatible Write Interface
Deep Power-Down Mode
0 05
mA
I
CC
Typical
0 8
mA
I
PP
Typical
12 0V
g
5% V
PP
Y
High-Performance Read
70 75 ns 90 ns 120 ns 150 ns
Maximum Access Time
5 0V
g
10% V
CC
Hardware Data Protection Feature
Erase Write Lockout during Power
Transitions
Advanced Packaging JEDEC Pinouts
32-Pin PDIP
32-Lead PLCC TSOP
ETOX
TM
II Nonvolatile Flash
Technology
EPROM-Compatible Process Base
High-Volume Manufacturing
Experience
Extended Temperature Options
Y
Y
Y
Y
Y
Y
Y
Y
Y
Intel鈥檚 28F001BX-B and 28F001BX-T combine the cost-effectiveness of Intel standard flash memory with
features that simplify write and allow block erase These devices aid the system designer by combining the
functions of several components into one making boot block flash an innovative alternative to EPROM and
EEPROM or battery-backed static RAM Many new and existing designs can take advantage of the
28F001BX鈥檚 integration of blocked architecture automated electrical reprogramming and standard processor
interface
The 28F001BX-B and 28F001BX-T are 1 048 576 bit nonvolatile memories organized as 131 072 bytes of
8 bits They are offered in 32-pin plastic DIP 32-lead PLCC and 32-lead TSOP packages Pin assignment
conform to JEDEC standards for byte-wide EPROMs These devices use an integrated command port and
state machine for simplified block erasure and byte reprogramming The 28F001BX-T鈥檚 block locations pro-
vide compatibility with microprocessors and microcontrollers that boot from high memory such as Intel鈥檚
MCS -186 family 80286 i386
TM
i486
TM
i860
TM
and 80960CA With exactly the same memory segmentation
the 28F001BX-B memory map is tailored for microprocessors and microcontrollers that boot from low memory
such as Intel鈥檚 MCS-51 MCS-196 80960KX and 80960SX families All other features are identical and unless
otherwise noted the term 28F001BX can refer to either device throughout the remainder of this document
The boot block section includes a reprogramming write lock out feature to guarantee data integrity It is
designed to contain secure code which will bring up the system minimally and download code to the other
locations of the 28F001BX Intel鈥檚 28F001BX employs advanced CMOS circuitry for systems requiring high-
performance access speeds low power consumption and immunity to noise Its access time provides
no-WAIT-state performance for a wide range of microprocessors and microcontrollers A deep-powerdown
mode lowers power consumption to 0 25
mW
typical through V
CC
crucial in laptop computer handheld instru-
mentation and other low-power applications The RP power control input also provides absolute data protec-
tion during system powerup or power loss
Manufactured on Intel鈥檚 ETOX process base the 28F001BX builds on years of EPROM experience to yield the
highest levels of quality reliability and cost-effectiveness
NOTE
The 28F001BN is equivalent to the 28F001BX
Other brands and names are the property of their respective owners
Information in this document is provided in connection with Intel products Intel assumes no liability whatsoever including infringement of any patent or
copyright for sale and use of Intel products except as provided in Intel鈥檚 Terms and Conditions of Sale for such products Intel retains the right to make
changes to these specifications at any time without notice Microcomputer Products may have minor variations to this specification known as errata
COPYRIGHT
INTEL CORPORATION 1995
November 1995
Order Number 290406-007

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