鈥?/div>
Supported PCI only functions:
-
-
-
-
NGO Netlist
Constraint Files
User Constraint Files (UCF)
Example Design
Verilog/VHDL Example Design
Design Tool Requirements
Xilinx Tools
v4.2i, Service Pack 3
Tested Entry and
Synplicity Synplify
Verification Tools
2
Synopsys FPGA Express
Exemplar Leonardo Spectrum
Xilinx XST
3
Cadence Verilog XL
Model Technology ModelSim
1. The resource utilization depends on configuration of the interface and the user
design. Unused resources are trimmed by the Xilinx technology mapper. The uti-
lization figures reported in this table are representative of a maximum configura-
tion.
2. See the implementation guide or product release notes for current supported ver-
sions.
3. XST is command line option only. See Implementation Guide for details.
漏 2002 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and further disclaimers are as listed at
http://www.xilinx.com/legal.htm.
All other
trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.
NOTICE OF DISCLAIMER: Xilinx is providing this design, code, or information "as is." By providing the design, code, or information as one possible implementation of this fea-
ture, application, or standard, Xilinx makes no representation that this implementation is free from any claims of infringement. You are responsible for obtaining any rights you may
require for your implementation. Xilinx expressly disclaims any warranty whatsoever with respect to the adequacy of the implementation, including but not limited to any warran-
ties or representations that this implementation is free from claims of infringement and any implied warranties of merchantability or fitness for a particular purpose.
DS 208 (v.1.2) June 28, 2002
Data Sheet, v3.0.99
www.xilinx.com
1-800-255-7778
1
1
2
3
4
5
