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DTC114YET1G Datasheet

  • DTC114YET1G

  • Bias Resistor Transistor

  • 10頁(yè)

  • ONSEMI

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DTC114EET1 Series
Bias Resistor Transistor
NPN Silicon Surface Mount Transistor
with Monolithic Bias Resistor Network
This new series of digital transistors is designed to replace a single
device and its external resistor bias network. The BRT (Bias Resistor
Transistor) contains a single transistor with a monolithic bias network
consisting of two resistors; a series base resistor and a base鈭抏mitter
resistor. The BRT eliminates these individual components by
integrating them into a single device. The use of a BRT can reduce
both system cost and board space. The device is housed in the
SC鈭?5/SOT鈭?16 package which is designed for low power surface
mount applications.
Features
http://onsemi.com
NPN SILICON
BIAS RESISTOR TRANSISTORS
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
Simplifies Circuit Design
Reduces Board Space
Reduces Component Count
The SC鈭?5/SOT鈭?16 Package Can be Soldered Using Wave or
Reflow
鈥?/div>
The Modified Gull鈭扺inged Leads Absorb Thermal Stress During
Soldering Eliminating the Possibility of Damage to the Die
鈥?/div>
Available in 8 mm, 7 inch/3000 Unit Tape & Reel
鈥?/div>
Pb鈭扚ree Packages are Available
MAXIMUM RATINGS
(T
A
= 25擄C unless otherwise noted)
Rating
Collector-Base Voltage
Collector-Emitter Voltage
Collector Current
Symbol
V
CBO
V
CEO
I
C
Value
50
50
100
Unit
Vdc
Vdc
mAdc
3
PIN 1
BASE
(INPUT)
PIN 3
COLLECTOR
(OUTPUT)
R1
R2
PIN 2
EMITTER
(GROUND)
MARKING
DIAGRAM
2
1
SC鈭?5/SOT鈭?16
CASE 463
STYLE 1
xx M
Maximum ratings are those values beyond which device damage can occur.
Maximum ratings applied to the device are individual stress limit values (not
normal operating conditions) and are not valid simultaneously. If these limits are
exceeded, device functional operation is not implied, damage may occur and
reliability may be affected.
xx = Specific Device Code
M = Date Code
THERMAL CHARACTERISTICS
Rating
Total Device Dissipation,
FR鈭? Board (Note 1) @ T
A
= 25擄C
Derate above 25擄C
Thermal Resistance,
Junction鈭抰o鈭扐mbient (Note 1)
Total Device Dissipation,
FR鈭? Board (Note 2) @ T
A
= 25擄C
Derate above 25擄C
Thermal Resistance,
Junction鈭抰o鈭扐mbient (Note 2)
Junction and Storage Temperature Range
1. FR鈭? @ Minimum Pad
2. FR鈭? @ 1.0
脳
1.0 Inch Pad
漏
Semiconductor Components Industries, LLC, 2005
ORDERING INFORMATION
See detailed ordering, marking, and shipping information in
the package dimensions section on page 2 of this data sheet.
Symbol
P
D
Value
200
1.6
Unit
mW
mW/擄C
擄C/W
R
qJA
P
D
600
300
2.4
R
qJA
T
J
, T
stg
400
鈭?5 to
+150
mW
mW/擄C
擄C/W
擄C
1
January, 2005 鈭?Rev. 6
Publication Order Number:
DTC114EET1/D

DTC114YET1G 產(chǎn)品屬性

  • 3,000

  • 分離式半導(dǎo)體產(chǎn)品

  • 晶體管(BJT) - 單路﹐預(yù)偏壓式

  • -

  • NPN - 預(yù)偏壓

  • 100mA

  • 50V

  • 10k

  • 47k

  • 80 @ 5mA，10V

  • 250mV @ 300µA，10mA

  • 500nA

  • -

  • 200mW

  • 表面貼裝

  • SC-75，SOT-416

  • SC-75，SOT-416

  • 帶卷 (TR)

  • DTC114YET1GOSDTC114YET1GOS-NDDTC114YET1GOSTR

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