鈥?/div>
Up to 40 MIPS operation at 80 MHz core
frequency
DSP and MCU functionality in a unified,
C-efficient architecture
MCU-friendly instruction set supports both
DSP and controller functions: MAC, bit
manipulation unit, 14 addressing modes
8K
脳
16-bit words Program Flash
1K
脳
16-bit words Program RAM
2K
脳
16-bit words Data Flash
1K
脳
16-bit words Data RAM
2K
脳
16-bit words Boot Flash
6
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
Hardware DO and REP loops
6-channel PWM Module
Two 4-channel, 12-bit ADCs
Serial Communications Interface (SCI)
Serial Peripheral Interface (SPI)
General Purpose Quad Timer
JTAG/OnCE
TM
port for debugging
On-chip relaxation oscillator
11 shared GPIO
48-pin LQFP Package
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
PWM Outputs
PWMA
RESET
IRQA
6
JTAG/
OnCE
Port
VCAPC V
DD
2
4
V
SS
5*
Digital Reg
Analog Reg
V
DDA
V
SSA
Fault Input
4
4
A/D1
A/D2
VREF
ADC
Interrupt
Controller
Low Voltage
Supervisor
Program Controller
and
Hardware Looping Unit
Address
Generation
Unit
Data ALU
16 x 16 + 36
鈫?/div>
36-Bit MAC
Three 16-bit Input Registers
Two 36-bit Accumulators
Bit
Manipulation
Unit
Quad Timer C
Quad Timer D
or GPIO
Program Memory
8188 x 16 Flash
1024 x 16 SRAM
Boot Flash
2048 x 16 Flash
Data Memory
2048 x 16 Flash
1024 x 16 SRAM
鈥?/div>
PAB
鈥?/div>
鈥?/div>
PDB
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
IPBB
CONTROLS
16
PLL
3
XDB2
CGDB
XAB1
XAB2
16-Bit
DSP56800
Core
Clock Gen
or Optional
Internal
Relaxation Osc.
GPIOB3/XTAL
GPIOB2/EXTAL
鈥?/div>
2
SCI0
or
GPIO
INTERRUPT
CONTROLS
16
COP/
Watchdog
COP RESET
MODULE CONTROLS
ADDRESS BUS [8:0]
DATA BUS [15:0]
4
SPI
or
GPIO
Application-
Specific
Memory &
Peripherals
IPBus Bridge
(IPBB)
*
includes TCS pin which is reserved for factory use and is tied to VSS
Figure 1. DSP56F801 Block Diagram
漏 Motorola, Inc., 2002. All rights reserved.
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