Freescale Semiconductor, Inc.
DSP56852/D
Rev. 6.0 2/2004
DSP56852
Preliminary Technical Data
DSP56852 16-bit Digital Signal Processor
鈥?120 MIPS at 120MHz
鈥?6K x 16-bit Program SRAM
鈥?4K x 16-bit Data SRAM
鈥?1K x 16-bit Boot ROM
鈥?Interrupt Controller
鈥?General Purpose 16-bit Quad Timer
鈥?JTAG/Enhanced On-Chip Emulation (OnCE鈩? for
unobtrusive, real-time debugging
鈥?Computer Operating Properly (COP)/Watchdog
Timer
鈥?81-pin MAPBGA package
鈥?Up to 11 GPIO
Freescale Semiconductor, Inc...
鈥?21 External Memory Address lines, 16 data lines
and four chip selects
鈥?One (1) Serial Port Interface (SPI) or one (1)
Improved Synchronous Serial Interface (ISSI)
鈥?One (1) Serial Communication Interface (SCI)
V
DDIO
6
6
V
DD
3
V
SSIO
6
V
SS
V
DDA
3
V
SSA
JTAG/
Enhanced
OnCE
Program Controller
and
Hardware Looping Unit
Address
Generation Unit
16-Bit
DSP56800E Core
Data ALU
16 x 16 + 36
鈫?/div>
36-Bit MAC
Three 16-bit Input Registers
Four 36-bit Accumulators
Bit
Manipulation
Unit
PAB
PDB
CDBR
CDBW
Memory
XDB2
R/W Control
XAB1
XAB2
PAB
PDB
Program Memory
6144 x 16 SRAM
Boot ROM
1024 x 16 ROM
Data Memory
4096 x 16 SRAM
System
Bus
Control
CDBR
CDBW
System
Address
Decoder
System
Device
IPBus Bridge (IPBB)
RW
Control
IPAB
IPWDB
IPRDB
Peripheral
Address
Decoder
Decoding
Peripherals
A0-16
A17-18 muxed (timer pins)
A19 muxed (CS3)
D0-D12[12:0]
D13-15 muxed (Mode A,B,C)
WR Enable
RD Enable
CS[2:0] muxed (GPIOA)
External Address
Bus Switch
External Data
Bus Switch
Bus Control
External Bus
Interface Unit
Peripheral
Device
Selects
Clock
resets
PLL
SCI or
GPIOE
1 Quad
Timer
or A17,
A18
2
SSI or
SPI or
GPIOC
COP/
Watch-
dog
Interrupt
Controller
P
O
R
System
Integration
Module
Clock
Generator
O
S
C
XTAL
EXTAL
2
6
IRQA
IRQB
3
CLKO
RESET
muxed
(A20)
MODE
muxed (D13-15)
Figure 1. DSP56852 Block Diagram
漏 Motorola, Inc., 2004. All rights reserved.
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