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DS96F175MW/883 Datasheet

  • DS96F175MW/883

  • Quad Differential Receivers

  • 241.98KB

  • 10頁

  • NSC

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DS96F173C/DS96F173M/DS96F175C/DS96F175M EIA-485/EIA-422 Quad Differential Receivers
May 1998
DS96F173C/DS96F173M/DS96F175C/DS96F175M
EIA-485/EIA-422 Quad Differential Receivers
General Description
The DS96F173 and the DS96F175 are high speed quad dif-
ferential line receivers designed to meet the EIA-485 stan-
dard. The DS96F173 and the DS96F175 offer improved per-
formance due to the use of L-FAST bipolar technology. The
use of LFAST technology allows the DS96F173 and
DS96F175 to operate at higher speeds while minimizing
power consumption.
The DS96F173 and the DS96F175 have TRI-STATE
廬
out-
puts and are optimized for balanced multipoint data bus
transmission at rates up to 15 Mbps. The receivers feature
high input impedance, input hysteresis for increased noise
immunity, and input sensitivity of 200 mV over a common
mode input voltage range of 鈭?V to +12V. The receivers are
therefore suitable for multipoint applications in noisy environ-
ments. The DS96F173 features an active high and active
low Enable, common to all four receivers. The DS96F175
features separate active high Enables for each receiver pair.
Features
n
n
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n
Meets EIA-485, EIA-422A, EIA-423A standards
Designed for multipoint bus applications
TRI-STATE outputs
Common mode input voltage range: 鈭?V to +12V
Operates from single +5.0V supply
Reduced power consumption (I
CC
= 50 mA max)
Input sensitivity of
鹵
200 mV over common mode range
Input hysteresis of 50 mV typical
High input impedance
Military temperature range available
Qualified for MIL STD 883C
Available to standard military drawings (SMD)
Available in DIP(J), LCC(E), and FlatPak (W) packages
DS96F173 and DS96F175 are lead and function
compatible with SN75173/175 or the
AM26LS32/MC3486
Logic Diagrams
Function Tables
(Each Receiver) DS96F173
Differential Inputs
A鈥揃
V
ID
鈮?/div>
0.2V
V
ID
鈮?/div>
鈭?.2V
DS009627-10
Enable
E
H
X
H
X
L
X
E
X
L
X
L
X
H
Output
Y
H
H
L
L
Z
Z
DS96F175
X
X
H = High Level
L = Low Level
Z = High Impedance (off)
X = Don鈥檛 Care
(Each Receiver) DS96F175
Differential Inputs
DS009627-11
Enable
E
H
H
L
Output
Y
H
L
Z
A鈥揃
V
ID
鈮?/div>
0.2V
V
ID
鈮?/div>
鈭?.2V
X
TRI-STATE
廬
is a registered trademark of National Semiconductor Corporation.
漏 1998 National Semiconductor Corporation
DS009627
www.national.com

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