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DS92LV16TVHG Datasheet

  • DS92LV16TVHG

  • 16-Bit Bus LVDS Serializer/Deserializer - 25 - 80 MHz

  • 19頁

  • NSC

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DS92LV1616-Bit Bus LVDS Serializer/Deserializer - 25 - 80 MHz
February 2002
DS92LV16
16-Bit Bus LVDS Serializer/Deserializer - 25 - 80 MHz
General Description
The DS92LV16 Serializer/Deserializer (SERDES) pair trans-
parently translates a 16鈥揵it parallel bus into a BLVDS serial
stream with embedded clock information. This single serial
stream simplifies transferring a 16-bit, or less bus over PCB
traces and cables by eliminating the skew problems between
parallel data and clock paths. It saves system cost by nar-
rowing data paths that in turn reduce PCB layers, cable
width, and connector size and pins.
This SERDES pair includes built-in system and device test
capability. The line loopback and local loopback features
provide the following functionality: the local loopback en-
ables the user to check the integrity of the transceiver from
the local parallel-bus side and the system can check the
integrity of the data transmission line by enabling the line
loopback.
The DS92LV16 incorporates BLVDS signaling on the high-
speed I/O. BLVDS provides a low power and low noise
environment for reliably transferring data over a serial trans-
mission path. The equal and opposite currents through the
differential data path control EMI by coupling the resulting
fringing fields together.
Features
n
25鈥?0 MHz 16:1/1:16 serializer/deserializer (2.56Gbps
full duplex throughput)
n
Independent transmitter and receiver operation with
separate clock, enable, power down pins
n
Hot plug protection (power up high impedance) and
synchronization (receiver locks to random data)
n
Wide +/鈭?% reference clock frequency tolerance for
easy system design using locally-generated clocks
n
Line and local loopback modes
n
Robust BLVDS serial transmission across backplanes
and cables for low EMI
n
No external coding required
n
Internal PLL, no external PLL components required
n
Single +3.3V power supply
n
Low power: 104mA (typ) transmitter, 119mA (typ)
receiver at 80MHz
n
100mV receiver input threshold
n
Loss of lock detection and reporting pin
n
Industrial 鈭?0 to +85藲C temperature range
n
>
2.5kV HBM ESD
n
Compact, standard 80-pin PQFP package
Block Diagram
DS92LV16
20014301
漏 2002 National Semiconductor Corporation
DS200143
www.national.com

DS92LV16TVHG 產(chǎn)品屬性

  • National Semiconductor (TI)

  • 1

  • 16

  • 2560 Mbps

  • 3.3 V

  • + 85 C

  • LQFP-80

  • Tray

  • - 40 C

  • SMD/SMT

  • 119

  • 3.45 V

  • 3.15 V

  • LVCMOS, LVTTL

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