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DS90LV028 Datasheet

  • DS90LV028

  • 3V LVDS Dual CMOS Differential Line Receiver

  • 10頁

  • NSC

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DS90LV028A 3V LVDS Dual CMOS Differential Line Receiver
June 1998
DS90LV028A
3V LVDS Dual CMOS Differential Line Receiver
General Description
The DS90LV028A is a dual CMOS differential line receiver
designed for applications requiring ultra low power dissipa-
tion, low noise and high data rates. The device is designed to
support data rates in excess of 400 Mbps (200 MHz) utilizing
Low Voltage Differential Signaling (LVDS) technology.
The DS90LV028A accepts low voltage (350 mV typical) dif-
ferential input signals and translates them to 3V CMOS out-
put levels. The receiver also supports open, shorted and ter-
minated (100鈩? input fail-safe. The receiver output will be
HIGH for all fail-safe conditions. The DS90LV028A has a
flow-through design for easy PCB layout.
The DS90LV028A and companion LVDS line driver provide a
new alternative to high power PECL/ECL devices for high
speed point-to-point interface applications.
Features
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400 Mbps (200 MHz) switching rates
50 ps differential skew (typical)
0.1 ns channel-to-channel skew (typical)
2.5 ns maximum propagation delay
3.3V power supply design
Flow-through pinout
Power down high impedance on LVDS inputs
Low Power design (18mW
@
3.3V static)
Interoperable with existing 5V LVDS networks
Accepts small swing (350 mV typical) differential signal
levels
Supports open, short and terminated input fail-safe
Conforms to ANSI/TIA/EIA-644 Standard
Industrial temperature operating range
(鈭?0藲C to +85藲C)
Available in SOIC package
Connection Diagram
Dual-in-Line
Functional Diagram
DS100077-1
Order Number DS90LV028ATM
See NS Package Number M08A
DS100077-2
Truth Table
INPUTS
[R
IN
+] 鈭?[R
IN
鈭抅
V
ID
鈮?/div>
0.1V
V
ID
鈮?/div>
鈭?.1V
Full Fail-safe
OPEN/SHORT
or Terminated
OUTPUT
R
OUT
H
L
H
漏 1998 National Semiconductor Corporation
DS100077
www.national.com

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