day鈥欌€?/div>
Data is transferred between the frequency synthesizer and
the controller via a 3 wire bus system This consists of a
data input line an enable line and a clock line When the
enable line is low data can be shifted from the controller
into the frequency synthesizer When the enable line is tran-
sitioned from low to high data entry is disabled and data
present in the shift register is latched
From the controller 22-bit data stream the first 2 bits ad-
dress the device permitting other devices to share the same
bus Of the remaining 20-bit data word the next 14-bits are
used for the PLL divide code The remaining 6 bits are con-
nected via latches to output pins These 6 bits can be used
to drive radio functions such as gain mute FM AM LW and
SW only These outputs are open collector Bit 18 is used
internally to select the AM or FM local oscillator input and to
select between the 500 Hz and 12 5 kHz reference A high
level at bit 18 indicates FM and a low level indicates AM
The PLL consists of a 14-bit programmable I
2
L divider an
ECL phase comparator an ECL dual modulus (p p
a
1)
prescaler and a high speed charge pump The programma-
ble divider divides by (N
a
1) N being the number loaded
into the shift register (bits 1鈥?4 after address) It is clocked
by the AM input via an ECL
d
7 8 prescaler or through a
d
63 64 prescaler from the FM input The AM input will work
at frequencies up to 8 MHz while the FM input works up to
120 MHz The AM band is tuned with a frequency resolution
of 500 Hz and the FM band is tuned with a resolution of 12 5
kHz The buffered AM and FM inputs are self-biased and
can be driven directly by the VCO thru a capacitor The ECL
phase comparator produces very accurate resolution of the
phase difference between the input signal and the reference
oscillator
The high speed charge pump consists of a switchable con-
stant current source (
b
0 3 mA) and a switchable constant
current sink (
a
0 3 mA) If the VCO frequency is low the
charge pump will source current and sink current if the VCO
frequency is high
A separate V
CCM
pin (typically drawing 1 5 mA) powers the
oscillator and reference chain to provide controller clocking
frequencies when the balance of the PLL is powered down
Features
Y
Y
Y
Y
Y
Y
Y
Uses inexpensive 4 MHz reference crystal
F
IN
capability greater than 120 MHz allows direct syn-
thesis at FM frequencies
FM resolution of 12 5 kHz allows usage of 10 7 MHz
ceramic filter distribution
Serial data entry for simplified control
50 Hz output for 鈥樷€榯ime-of-day鈥欌€?reference with separate
low power supply (V
CCM
)
6-open collector buffered outputs for band switching
and other radio functions
Separate AM and FM inputs AM input has 15 mV (typi-
cal) hysteresis
Connection Diagram
Dual-In-Line Package
TL F 5775 鈥?1
Top View
Order Number DS8906N
See NS Package Number N20A
TRI-STATE is a registered trademark of National Semiconductor Corp
C
1995 National Semiconductor Corporation
TL F 5775
RRD-B30M105 Printed in U S A
1
2
3
4
5
6
7
8
