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DS8641N Datasheet

  • DS8641N

  • Quad Unified Bus Transceiver

  • 5頁

  • NSC

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DS8641 Quad Unified Bus Transceiver
January 1996
DS8641
Quad Unified Bus Transceiver
General Description
The DS8641 is a quad high speed drivers/receivers de-
signed for use in bus organized data transmission systems
interconnected by terminated 120鈩?impedance lines. The
external termination is intended to be a 180鈩?resistor from
the bus to the +5V logic supply together with a 390鈩?resistor
from the bus to ground. The bus can be terminated at one or
both ends. Low bus pin current allows up to 27 driver/
receiver pairs to utilize a common bus. The bus loading is
unchanged when V
CC
= 0V. The receivers incorporate tight
thresholds for better bus noise immunity. One two-input NOR
gate is included to disable all drivers in a package simulta-
neously.
Features
n
4 separate driver/receiver pairs per package
n
Guaranteed minimum bus noise immunity of 0.6V, 1.1V
typ
n
Temperature insensitive receiver thresholds track bus
logic levels
n
30 碌A(chǔ) typical bus terminal current with normal V
CC
or
with V
CC
= 0V
n
Open collector driver output allows wire-OR connection
n
High speed
n
Series 74 TTL compatible driver and disable inputs and
receiver outputs
Connection Diagram
Dual-In-Line Package
DS005806-1
Top View
Order Number DS8641N
See NS Package Number N16A
漏 1999 National Semiconductor Corporation
DS005806
www.national.com

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