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DS78LS120J/883 Datasheet

  • DS78LS120J/883

  • Dual Differential Line Receiver (Noise Filtering and Fail-Sa...

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DS78LS120 Dual Differential Line Receiver (Noise Filtering and Fail-Safe)
September 1999
DS78LS120
Dual Differential Line Receiver (Noise Filtering and
Fail-Safe)
General Description
The DS78LS120 is a high performance, dual differential, TTL
compatible line receiver for both balanced and unbalanced
digital data transmission. The inputs are compatible with
EIA, Federal and MIL standards.
The line receiver will discriminate a
鹵
200 mV input signal
over a common-mode range of
鹵
10V and a
鹵
300 mV signal
over a range of
鹵
15V.
Circuit features include hysteresis and response control for
applications where controlled rise and fall times and/or high
frequency noise rejection are desirable. Threshold offset
control is provided for fail-safe detection, should the input be
open or short. Each receiver includes an optional 180鈩?/div>
terminating resistor and the output gate contains a logic
strobe for time discrimination. The DS78LS120 is specified
over a 鈭?5藲C to +125藲C temperature range.
Input specifications meet or exceed those of the popular
DS7820 line receiver.
Features
n
Meets EIA standards RS232-C, RS422 and RS423,
Federal Standards 1020, 1030 and MIL-188-114
n
Input voltage range of
鹵
15V (differential or
common-mode)
n
Separate strobe input for each receiver
n
5k typical input impedance
n
Optional 180鈩?termination resistor
n
50mV input hysteresis
n
200mV input threshold
n
Separate fail-safe mode
Connection Diagram
Dual-In-Line-Package
00749901
Top View
see RETS Data Sheet.
Order Number DS78LS120J/883 or DS78LS120W/883
See NS Package Number J16A or W16A
漏 2004 National Semiconductor Corporation
DS007499
www.national.com

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DS78LS120J/883相關(guān)型號(hào)PDF文件下載

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  • 英文版
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    Dual Line Receiver
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    Dual Line Receiver
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    Dual Line Receiver
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    Dual Differential Line Driver
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    Quad TRI-STATE Bus Transceivers
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    Quad NOR Unified Bus Receiver
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