DS3886A BTL 9-Bit Latching Data Transceiver
June 1998
DS3886A
BTL 9-Bit Latching Data Transceiver
General Description
The DS3886A is a higher speed, lower power, pin compat-
ible version of the DS3886.
The DS3886A is one in a series of transceivers designed
specifically for the implementation of high performance Fu-
turebus+ and proprietary bus interfaces. The DS3886A is a
BTL 9-Bit Latching Data Transceiver designed to conform to
IEEE 1194.1 (Backplane Transceiver Logic 鈥?BTL) as speci-
fied in the IEEE 896.2 Futurebus+ specification. The
DS3886A incorporates an edge-triggered latch in the driver
path which can be bypassed during fall-through mode of op-
eration and a transparent latch in the receiver path. Utiliza-
tion of the DS3886A simplifies the implementation of byte
wide address/data with parity lines and also may be used for
the Futurebus+ status, tag and command lines.
The DS3886A driver output configuration is an NPN open
collector which allows Wired-OR connection on the bus.
Each driver output incorporates a Schottky diode in series
with it鈥檚 collector to isolate the transistor output capacitance
from the bus, thus reducing the bus loading in the inactive
state. The combined output capacitance of the driver output
and receiver input is less than 5 pF. The driver also has high
sink current capability to comply with the bus loading re-
quirements defined within IEEE 1194.1 BTL specification.
Backplane Transceiver Logic (BTL) is a signaling standard
that was invented and first introduced by National Semicon-
ductor, then developed by the IEEE to enhance the perfor-
mance of backplane buses. BTL compatible transceivers
feature low output capacitance drivers to minimize bus load-
ing, a 1V nominal signal swing for reduced power consump-
tion and receivers with precision thresholds for maximum
noise immunity. The BTL standard eliminates settling time
delays that severely limit TTL bus performance, and thus
provide significantly higher bus transfer rates. The back-
plane bus is intended to be operated with termination resis-
tors (selected to match the bus impedance) connected to
2.1V at both ends. The low voltage is typically 1V.
Separate ground pins are provided for each BTL output to
minimize induced ground noise during simultaneous switch-
ing.
The unique driver circuitry meets the maximum slew rate of
0.5 V/ns which allows controlled rise and fall times to reduce
noise coupling to adjacent lines.
The transceiver鈥檚 high impedance control and driver inputs
are fully TTL compatible.
The receiver is a high speed comparator that utilizes a Band-
gap reference for precision threshold control, allowing maxi-
mum noise immunity to the BTL 1V signaling level. Separate
QV
CC
and QGND pins are provided to minimize the effects
of high current switching noise. The output is TRI-STATE
廬
and fully TTL compatible.
The DS3886A supports live insertion as defined in IEEE
896.2 through the LI (Live Insertion) pin. To implement live
insertion the LI pin should be connected to the live insertion
TRI-STATE
廬
is a registered trademark of National Semiconductor Corporation.
power connector. If this function is not supported, the LI pin
must be tied to the V
CC
pin. The DS3886A also provides
glitch free power up/down protection during power sequenc-
ing.
The DS3886A has two types of power connections in addi-
tion to the LI pin. They are the Logic V
CC
(V
CC
) and the Quiet
V
CC
(QV
CC
). There are two Logic V
CC
pins on the DS3886A
that provide the supply voltage for the logic and control cir-
cuitry. Multiple connections are provided to reduce the ef-
fects of package inductance and thereby minimize switching
noise. As these pins are common to the V
CC
bus internal to
the device, a voltage delta should never exist between these
pins and the voltage difference between V
CC
and QV
CC
should never exceed
鹵
0.5V because of ESD circuitry.
When CD (Chip Disable) is high, An is in high impedance
state and Bn is high. To transmit data (An to Bn) the T/R sig-
nal is high.
When RBYP is high, the positive edge triggered flip-flop is in
the transparent mode. When RBYP is low, the positive edge
of the ACLK signal clocks the data.
In addition, the ESD circuitry between the V
CC
pins and all
other pins except for BTL I/O鈥檚 and LI pins requires that any
voltage on these pins should not exceed the voltage on V
CC
+0.5V.
There are three different types of ground pins on the
DS3886A; the logic ground (GND), BTL grounds
(B0GND鈥揃8GND) and the Bandgap reference ground
(QGND). All of these ground reference pins are isolated
within the chip to minimize the effects of high current switch-
ing transients. For optimum performance the QGND should
be returned to the connector through a quiet channel that
does not carry transient switching current. The GND and
B0GND鈥揃8GND should be connected to the nearest back-
plane ground pin with the shortest possible path.
Since many different grounding schemes could be imple-
mented and ESD circuitry exists on the DS3886A, it is impor-
tant to note that any voltage difference between ground pins,
QGND, GND or B0GND鈥揃8GND should not exceed
鹵
0.5V
including power up/down sequencing.
The DS3886A is offered in 44-pin PLCC, and 44-pin PQFP
high density package styles.
Features
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Fast propagation delay (3ns typ)
9-BIT BTL Latched Transceiver
Driver incorporates edge triggered latches
Receiver incorporates transparent latches
Meets IEEE 1194.1 Standard on Backplane Transceiver
Logic (BTL)
Supports Live Insertion
Glitch free Power-up/down protection
Typically less than 5 pF Bus-port capacitance
Low Bus-port voltage swing (typically 1V) at 80 mA
漏 1999 National Semiconductor Corporation
DS011458
www.national.com
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