DS3883A BTL 9-Bit Data Transceiver
July 1998
DS3883A
BTL 9-Bit Data Transceiver
General Description
The DS3883A is one in a series of transceivers designed
specifically for the implementation of high performance Fu-
turebus+ and proprietary bus interfaces. The DS3883A, is a
BTL 9-bit Transceiver designed to conform to IEEE 1194.1
(Backplane Transceiver Logic 鈥?BTL) as specified in the
IEEE 896.2 Futurebus+ specification. Utilization of the
DS3883A simplifies the implementation of byte wide
address/data with parity lines and also may be used for the
Futurebus+ status, tag and command lines.
The DS3883A driver output configuration is an NPN open
collector which allows Wired-OR connection on the bus.
Each driver output incorporates a Schottky diode in series
with its collector to isolate the transistor output capacitance
from the bus thus reducing the bus loading in the inactive
state. The combined output capacitance of the driver and re-
ceiver input is less than 5 pF. The driver also has high sink
current capability to comply with the bus loading require-
ments defined within IEEE 1194.1 BTL specification.
Backplane Transceiver Logic (BTL) is a signaling standard
that was invented and first introduced by National Semicon-
ductor, then developed by the IEEE to enhance the perfor-
mance of backplane buses. BTL compatible transceivers
feature low output capacitance drivers to minimize bus load-
ing, a 1V nominal signal swing for reduced power consump-
tion and receivers with precision thresholds for maximum
noise immunity. BTL eliminates settling time delays that se-
verely limit TTL bus performance, and thus provide signifi-
cantly higher bus transfer rates. The backplane bus is in-
tended to be operated with termination resistors (selected to
match the bus impedance) connected to 2.1V at both ends.
The low voltage is typically 1V.
Separate ground pins are provided for each BTL output to
minimize induced ground noise during simultaneous switch-
ing.The unique driver circuitry meets the maximum slew rate
of 0.5 V/ns which allows controlled rise and fall times to re-
duce noise coupling to adjacent lines.The transceiver鈥檚 con-
trol and driver inputs are designed with high impedance PNP
input structures and are fully TTL compatible.
The receiver is a high speed comparator that utilizes a band-
gap reference for precision threshold control allowing maxi-
mum noise immunity to the BTL 1V signaling level. Separate
QV
CC
and QGND pins are provided to minimize the effects
of high current switching noise. The output is TRI-STATE
廬
and fully TTL compatible.
The DS3883A supports live insertion as defined in 896.2
through the LI (Live Insertion) pin. To implement live inser-
tion the LI pin should be connected to the live insertion
power connector. If this function is not supported the LI pin
must be tied to the V
CC
pin. The DS3883A also provides
glitch free power up/down protection during power sequenc-
ing.
The DS3883A has two types of power connections in addi-
tion to the LI pin. They are the Logic V
CC
(V
CC
) and the Quiet
V
CC
(QV
CC
). There are two logic V
CC
pins on the DS3883
that provide the supply voltage for the logic and control cir-
cuitry. Multiple power pins reduce the effects of package in-
ductance and thereby minimize switching noise. As these
pins are common to the V
CC
bus internal to the device, a
voltage delta should never exist between these pins and the
voltage difference between V
CC
and QV
CC
should never ex-
ceed
鹵
0.5V because of ESD circuitry.
Additionally, the ESD circuitry between the V
CC
pins and all
other pins except for BTL I/O鈥檚 and LI pins requires that any
voltage on these pins should not exceed the voltage on V
CC
+ 0.5V.
There are three different types of ground pins on the
DS3883A. They are the logic ground (GND), BTL grounds
(B0GND鈥揃8GND) and the Bandgap reference ground
(QGND). All of these ground reference pins are isolated
within the chip to minimize the effects of high current switch-
ing transients. For optimum performance the QGND should
be returned to the connector through a quiet channel that
does not carry transient switching current. The GND and
B0GND鈥揃8GND should be connected to the nearest back-
plane ground pin with the shortest possible path.
Since many different grounding schemes could be imple-
mented and ESD circuitry exists on the DS3883, it is impor-
tant to note that any voltage difference between ground pins,
QGND, GND or B0GND鈥揃8GND should not exceed
鹵
0.5V
including power-up/down sequencing.
When CD (Chip Disable) is high, An and Bn are in a high im-
pedance state. To transmit data (An to Bn) the T/R signal is
high. To receive data (Bn to An) the T/R signal is low.
Features
n
9-bit Inverting BTL transceiver meets IEEE 1194.1
standard on Backplane Transceiver Logic (BTL)
n
Supports live insertion
n
Glitch free power-up/down protection
n
Typically less than 5 pF bus-port capacitance
n
Low bus-port voltage swing (typically 1V) at 80 mA
n
Open collector bus-port output allows Wired-OR
n
Controlled rise and fall time to reduce noise coupling
n
TTL compatible driver and control inputs
n
Built in bandgap reference with separate QV
CC
and
QGND pins for precise receiver thresholds
n
Exceeds 2 kV ESD (Human Body Model)
n
Individual bus-port ground pins minimize ground bounce
n
Tight skew (1 ns typical)
TRI-STATE
廬
is a registered trademark of National Semiconductor Corporation.
漏 1999 National Semiconductor Corporation
DS010719
www.national.com
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