loads associated with MOS memory systems The drivers鈥?/div>
output (V
OH
) is specified at 3 4V to provide additional noise
immunity required by MOS inputs A PNP input structure is
employed to minimize input currents The circuit employs
Schottky-clamped transistors for high speed A NOR gate of
two inputs DIS1 and DIS2 controls the TRI-STATE mode
Features
Y
Y
Y
Y
Y
Y
High speed capabilities
Typical 5 ns driving 50 pF 8 ns driving 500 pF
TRI-STATE outputs
High V
OH
(3 4V min)
High density
Eight drivers and two disable controls for TRI-STATE
in a 20-pin package
PNP inputs reduce DC loading on bus lines
Glitch-free power up down
Schematic and Connection Diagrams
Dual-In-Line Package
Top View
TL F 5875 鈥?1
TL F 5875 鈥?2
(Equivalent Input Output Circuit)
Order Number
DS1628J DS3628J DS3628N
See NS Package Number J20A or N20A
Truth Table
Disable Input
DIS 1
H
H
X
L
L
H
e
high level
L
e
low level
X
e
don鈥檛 care
Z
e
high impedance (off)
Typical Application
Input
X
X
X
H
L
Output
Z
Z
Z
L
H
DIS 2
H
X
H
L
L
TL F 5875 鈥?3
TRI-STATE is a registered trademark of National Semiconductor Corp
C
1995 National Semiconductor Corporation
TL F 5875
RRD-B30M115 Printed in U S A