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DS34LV86TN Datasheet

  • DS34LV86TN

  • 3V Enhanced CMOS Quad Differential Line Receiver

  • 195.70KB

  • 10頁

  • NSC

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DS34LV86T 3V Enhanced CMOS Quad Differential Line Receiver
February 1997
DS34LV86T
3V Enhanced CMOS Quad Differential Line Receiver
General Description
The DS34LV86T is a high speed quad differential CMOS re-
ceiver that meets the requirements of both TIA/EIA-422-B
and ITU-T V.11. The CMOS DS34LV86T features typical low
static I
CC
of 9 mA which makes it ideal for battery powered
and power conscious applications. The TRI-STATE
廬
en-
ables, EN, allow the device to be disabled when not in use to
minimize power consumption. The dual enable scheme al-
lows for flexibility in turning receivers on and off.
The receiver output (RO) is guaranteed to be High when the
inputs are left open. The receiver can detect signals as low
as
鹵
200 mV over the common mode range of
鹵
10V. The re-
ceiver outputs (RO) are compatible with TTL and LVCMOS
levels.
Features
n
n
n
n
n
n
n
n
n
Low power CMOS design (30 mW typical)
Interoperable with existing 5V RS-422 networks
Industrial temperature range
Meets TIA/EIA-422-B (RS-422) and ITU-T V.11
recommendation
3.3V Operation
鹵
7V common mode range V
ID
= 3V
鹵
10V common mode range V
ID
= 0.2V
Receiver OPEN input failsafe feature
Guaranteed AC parameter:
Maximum Receiver Skew: 4 ns
Transition time: 10 ns
Pin compatible with DS34C86T
32 MHz Toggle Frequency
6.5k ESD Tolerance (HBM)
Available in SOIC packaging
n
n
n
n
Connection Diagram
Dual-In-Line Package
Truth Table
Enable
EN
L
H
H
H
L = Logic Low
H = Logic High
X = Irrelevant
Z = TRI-STATE
鈥?/div>
= Open, Not Terminated
Inputs
RI+鈥揜I鈭?/div>
X
V
ID
鈮?/div>
+0.2V
V
ID
鈮?/div>
鈭?.2V
Open
鈥?/div>
Output
RO
Z
H
L
H
DS012644-1
Top View
Order Number DS34LV86TN, DS34LV86TM
See NS Package Number M16A or N16E
TRI-STATE
廬
is a registered trademark of National Semiconductor Corporation.
漏 1998 National Semiconductor Corporation
DS012644
www.national.com

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