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DS31256 Datasheet

  • DS31256

  • 256-Channel, High-Throughput HDLC Controller

  • 1449.21KB

  • 183頁(yè)

  • MAXIM   MAXIM

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DEMO KIT AVAILABLE
DS31256
256-Channel, High-Throughput
HDLC Controller
www.maxim-ic.com
GENERAL DESCRIPTION
The DS31256 Envoy is a 256-channel HDLC
controller that can handle up to 60 T1 or 64 E1
data streams or two T3 data streams. Each of the
16 physical ports can handle one, two, or four
T1 or E1 data streams. The DS31256 is
composed of the following blocks: Layer 1,
HDLC processing, FIFO, DMA, PCI bus, and
local bus.
There are 16 HDLC engines (one for each port)
that are each capable of operating at speeds up
to 8.192Mbps in channelized mode and up to
10Mbps in unchannelized mode. The DS31256
Envoy also has three fast HDLC engines that
only reside on Ports 0, 1, and 2. They are
capable of operating at speeds up to 52Mbps.
FEATURES
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256 Independent, Bidirectional HDLC
Channels
Up to 132Mbps Full-Duplex Throughput
Supports Up to 60 T1 or 64 E1 Data Streams
16 Physical Ports (16 Tx and 16 Rx) That
Can Be Independently Configured for
Channelized or Unchannelized Operation
Three Fast (52Mbps) Ports; Other Ports
Capable of Speeds Up to 10Mbps
(Unchannelized)
Channelized Ports Can Each Handle One,
Two, or Four T1 or E1 Lines
Per-Channel DS0 Loopbacks in Both
Directions
Over-Subscription at the Port Level
Transparent Mode Supported
On-Board Bit Error-Rate Tester (BERT)
with Automatic Error Insertion Capability
BERT Function Can Be Assigned to Any
HDLC Channel or Any Port
Large 16kB FIFO in Both Receive and
Transmit Directions
Efficient Scatter/Gather DMA Maximizes
Memory Efficiency
Receive Data Packets are Time-Stamped
Transmit Packet Priority Setting
V.54 Loopback Code Detector
Local Bus Allows for PCI Bridging or Local
Access
Intel or Motorola Bus Signals Supported
Backward Compatibility with DS3134
33MHz 32-Bit PCI (V2.1) Interface
3.3V Low-Power CMOS with 5V Tolerant
I/O
JTAG Support IEEE 1149.1
256-Pin Plastic BGA (27mm x 27mm)
Features continued on page 6.
APPLICATIONS
Channelized and Clear-Channel
(Unchannelized) T1/E1 and T3/E3
Routers with Multilink PPP Support
High-Density Frame-Relay Access
xDSL Access Multiplexers (DSLAMs)
Triple HSSI
High-Density V.35
SONET/SDH EOC/ECC Termination
ORDERING INFORMATION
PART
DS31256
TEMP RANGE
0擄C to +70擄C
PIN-PACKAGE
256 PBGA
Note:
Some revisions of this device may incorporate deviations from published specifications known as errata. Multiple revisions of any device
may be simultaneously available through various sales channels. For information about device errata, click here:
www.maxim-ic.com/errata.
1 of 183
REV: 031405

DS31256 產(chǎn)品屬性

  • Lead (SnPb) Finish for COTSObsolescence Mitigation Program

  • 40

  • 集成電路 (IC)

  • 接口 - 控制器

  • -

  • HDLC 控制器

  • 串行

  • 3 V ~ 3.6 V

  • 500mA

  • 0°C ~ 70°C

  • 表面貼裝

  • 256-BBGA

  • 256-BGA（27x27）

  • 管件

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