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DS2172TN Datasheet

  • DS2172TN

  • Bit Error Rate Tester BERT

  • 21頁(yè)

  • DALLAS   DALLAS

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DS2172
Bit Error Rate Tester (BERT)
www.dalsemi.com
FEATURES
Generates/Detects digital bit patterns for
analyzing, evaluating and troubleshooting
digital communications systems
Operates at speeds from DC to 52 MHz
Programmable polynomial length and
feedback taps for generation of any other
pseudorandom pattern up to 32 bits in length
including: 2
6
-1, 2
9
-1, 2
11
-1, 2
15
-1, 2
20
-1, 2
23
-1,
and 2
32
-1
Programmable user-defined pattern and
length for generation of any repetitive pattern
up to 32 bits in length
Large 32-bit error count and bit count
registers
Software programmable bit error insertion
Fully independent transmit and receive
sections
8-bit parallel control port
Detects test patterns with bit error rates up to
10
-2
PIN ASSIGNMENT
TDATA
TDIS
TCLK
VSS
VDD
RCLK
RDIS
RDATA
32 31 30 29 28 27 26 25
TL
AD0
AD1
TEST
VSS
AD2
AD3
AD4
1
2
3
4
5
6
7
8
DS2172
32-Pin TQFP
24
23
22
21
20
19
18
17
RL
RLOS
LC
VSS
VDD
INT
WR(R/W)
ALE(AS)
9 10 11 12 13 14 15 16
ORDERING INFORMATION
DS2172T
DS2172TN
(0
0
C to 70
0
C)
(-40
0
C to + 85
0
C)
DESCRIPTION
The DS2172 Bit Error Rate Tester (BERT) is a software programmable test pattern generator, receiver,
and analyzer capable of meeting the most stringent error performance requirements of digital
transmission facilities. Two categories of test pattern generation (Pseudo-random and Repetitive)
conform to CCITT/ITU O.151, O.152, O.153, and O.161 standards. The DS2172 operates at clock rates
ranging from DC to 52 MHz. This wide range of operating frequency allows the DS2172 to be used in
existing and future test equipment, transmission facilities, switching equipment, multiplexers, DACs,
Routers, Bridges, CSUs, DSUs, and CPE equipment.
The DS2172 user-programmable pattern registers provide the unique ability to generate loopback patterns
required for T1, Fractional-T1, Smart Jack, and other test procedures. Hence the DS2172 can initiate the
loopback, run the test, check for errors, and finally deactivate the loopback.
The DS2172 consists of four functional blocks: the pattern generator, pattern detector, error counter, and
control interface. The DS2172 can be programmed to generate any pseudorandom pattern with length up
to 2
32
-1 bits (see Table 5, Note 9) or any user programmable bit pattern from 1 to 32 bits in length. Logic
inputs can be used to configure the DS2172 for applications requiring gap clocking such as Fractional-T1,
Switched-56, DDS, normal framing requirements, and per-channel test procedures. In addition, the
DS2172 can insert single or 10
-1
to 10
-7
bit errors to verify equipment operation and connectivity.
1 of 21
051700
AD5
AD6
AD7
VSS
VDD
BTS
RD(DS)
CS

DS2172TN 產(chǎn)品屬性

  • Lead (SnPb) Finish for COTS

  • 250

  • 集成電路 (IC)

  • 接口 - 電信

  • -

  • 位誤碼率測(cè)試器（BERT）

  • T1

  • 1

  • 4.5 V ~ 5.5 V

  • 10mA

  • -

  • -40°C ~ 85°C

  • 表面貼裝

  • 32-TQFP

  • 32-TQFP（7x7）

  • 管件

  • 錯(cuò)誤計(jì)數(shù)器，樣式發(fā)生器和檢測(cè)器

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