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DS21448LN Datasheet

  • DS21448LN

  • 3.3V E1/T1/J1 Quad Line Interface

  • 60頁

  • DALLAS   DALLAS

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DS21448
3.3V E1/T1/J1 Quad Line Interface
www.maxim-ic.com
GENERAL DESCRIPTION
The DS21448 is a quad-port E1 or T1 line interface
unit (LIU) for short-haul and long-haul applications. It
incorporates four independent transmitters and four
independent receivers in a single 144-pin PBGA or
128-pin LQFP package.
The transmit drivers generate the necessary G.703
E1 waveshapes in 75W or 120W applications and the
DSX-1 or CSU line build-outs of 0dB, -7.5dB, -15dB,
and -22.5dB for T1 applications.
The DS21448 has a usable receiver sensitivity of
0 to -43dB for E1 applications and 0 to -36dB for T1
that allows it to operate on 0.63mm (22AWG) cables
up to 2.5km (E1) and 6000ft (T1) in length. The user
has the option to use internal receive termination,
software selectable for 75W, 100W, and 120W
applications, or external termination.
The on-board crystal-less jitter attenuator can be
placed in either the transmit or the receive data path,
and requires only a 2.048MHz MCLK for both E1 and
T1 applications (with the option of using a 1.544MHz
MCLK in T1 applications).
The DS21448 has diagnostic capabilities such as
loopbacks and PRBS pattern generation and
detection. 16-bit loop-up and loop-down codes can
be generated and detected. A single input pin can
power down all transmitters to allow the
implementation of hitless protection switching (HPS)
for 1+1 redundancy without the use of relays.
The device can be controlled through an 8-bit parallel
port (muxed or nonmuxed) or a serial port, and it can
be used in hardware mode. A standard boundary
scan interface supports board-level testing.
FEATURES
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Four Complete E1, T1, or J1 LIUs
Supports Long- and Short-Haul Trunks
Internal Software-Selectable Receive-Side
Termination for 75W/100W/120W
3.3V Power Supply
32-Bit or 128-Bit Crystal-Less Jitter Attenuator
Requires Only a 2.048MHz Master Clock for E1
and T1, with the Option to Use 1.544MHz for T1
Generates the Appropriate Line Build-Outs With
and Without Return Loss for E1, and DSX-1 and
CSU Line Build-Outs for T1
AMI, HDB3, and B8ZS Encoding/Decoding
16.384MHz, 8.192MHz, 4.096MHz, or 2.048MHz
Clock Output Synthesized to Recovered Clock
Programmable Monitor Mode for Receiver
Loopbacks and PRBS Pattern Generation/
Detection with Output for Received Errors
Generates/Detects In-Band Loop Codes, 1 to 16
Bits, Including CSU Loop Codes
8-Bit Parallel or Serial Interface with Optional
Hardware Mode
Muxed and Nonmuxed Parallel Bus Supports
Intel or Motorola
Detects/Generates Blue (AIS) Alarms
NRZ/Bipolar Interface for Tx/Rx Data I/O
Transmit Open-Circuit Detection
Receive Carrier Loss (RCL) Indication (G.775)
High-Z State for TTIP and TRING
50mA
RMS
Transmit Current Limiter
JTAG Boundary Scan Test Port per IEEE 1149.1
Meets Latest E1 and T1 Specifications Including
ANSI.403-1999, ANSI T1.408, AT&T TR 62411,
ITU G.703, G.704, G.706, G.736, G.775, G.823,
I.431, O.151, O.161, ETSI ETS 300 166,
JTG.703, JTI.431, TBR12, TBR13, and CTR4
APPLICATIONS
Integrated Multiservice Access Platforms
T1/E1 Cross-Connects, Multiplexers, and Channel
Banks
Central-Office Switches and PBX Interfaces
T1/E1 LAN/WAN Routers
Wireless Base Stations
ORDERING INFORMATION
PART
DS21448
DS21448N
DS21448L
DS21448LN
TEMP RANGE
0擄C to +70擄C
-40擄C to +85擄C
0擄C to +70擄C
-40擄C to +85擄C
VOLTAGE
(V)
3.3
3.3
3.3
3.3
PIN-
PACKAGE
144 BGA
144 BGA
128 LQFP
128 LQFP
Pin Configurations appear in Section
11.
Note:
Some revisions of this device may incorporate deviations from published specifications known as errata. Multiple revisions of any device
may be simultaneously available through various sales channels. For information about device errata, click here:
www.maxim-ic.com/errata.
1 of 60
REV: 012104

DS21448LN 產(chǎn)品屬性

  • Maxim Integrated Products

  • Framer

  • 4

  • 400 mA

  • + 85 C

  • SMD/SMT

  • LQFP-128

  • - 40 C

  • 3.3 V

  • 3.465 V

  • 3.135 V

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