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DS1706T Datasheet

  • DS1706T

  • 3.3 and 5.0 Volt MicroMonitor

  • 10頁

  • DALLAS   DALLAS

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DSDS1705/DS1706
DS1705/DS1706
3.3 and 5.0 Volt MicroMonitor
FEATURES
PIN ASSIGNMENT
PBRST
1
2
3
4
8
7
6
5
WDS
RST
ST
NMI
鈥?/div>
Halts and restarts an out鈥搊f鈥揷ontrol microprocessor
鈥?/div>
Holds
sients
microprocessor in check during power tran-
restarts microprocessor after power
V
CC
GND
IN
鈥?/div>
Automatically
failure
鈥?/div>
Monitors pushbutton for external override
鈥?/div>
Accurate 5%, 10% or 20% resets for 3.3 systems and
5% or 10% resets for 5.0 volt systems
PBRST
V
CC
GND
IN
8鈥揚IN DIP
(300 MIL)
1
2
3
4
8
7
6
5
WDS
RST (*RST)
ST
NMI
鈥?/div>
Eliminates the need for discrete components
鈥?/div>
3.3 volt 20% tolerance for use with 3.0 volt systems
鈥?/div>
Pin compatible with the MAXIM MAX705/MAX706 in
8鈥損in DIP and 8鈥損in SOIC
8鈥揚IN SOIC
(150 MIL)
PBRST
VCC
GND
IN
1
2
3
4
8
7
6
5
WDS
RST (*RST)
ST
NMI
鈥?/div>
8鈥損in DIP, 8鈥損in SOIC and 8鈥損in
碌鈥揝OP
packages
鈥?/div>
Industrial temperature range 鈥?0擄C to +85擄C
8鈥揚IN
碌鈥揝OP
(118 MIL)
See Mech. Drawings
Section
DS1705 and DS1706_/R/S/T (*DS1706L and DS1706P)
PIN DESCRIPTION
PBRST
V
CC
GND
IN
NMI
ST
RST
*RST
WDS
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
Pushbutton Reset Input
Power Supply
Ground
Input
Non鈥搈askable Interrupt
Strobe Input
Active Low Reset Output
Active High Reset Output
(DS1706P and DS1706L only)
鈥?Watchdog Status Output
DESCRIPTION
The DS1705/DS1706 3.3 or 5.0 Volt MicroMonitor moni-
tors three vital conditions for a microprocessor: power
supply, software execution, and external override. A
precision temperature compensated reference and
comparator circuit monitors the status of V
CC
at the
device and at an upstream point for maximum protec-
tion. When the sense input detects an out鈥搊f鈥搕olerance
condition a non鈥搈askable interrupt is generated. As
the voltage at the device degrades an internal power fail
signal is generated which forces the reset to an active
state. When V
CC
returns to an in鈥搕olerance condition,
the reset signal is kept in the active state for a minimum
of 130 ms to allow the power supply and processor to
stabilize.
ECopyright
1995 by Dallas Semiconductor Corporation.
All Rights Reserved. For important information regarding
patents and other intellectual property rights, please refer to
Dallas Semiconductor data books.
011296 1/10

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